Cell disassembly device, cell disassembly method and computer-readable recording medium in which program for making computer execute the method is recorded

ABSTRACT

In a cell assembly and disassembly device having a cell disassembly unit ( 2 ) for disassembling the cell received from an ATM circuit interface, extracting data from the payload, distributing the data in plural time slots divided and multiplexed in time in frame period, and sending out to an STM circuit interface, the cell disassembly unit ( 2 ) comprises a fluctuation absorption buffer unit ( 11 ) provided in each time slot, and the data distributed in each time slot is once held in these buffers to absorb cell fluctuations, thereby suppressing both increase of total capacity of the memory for absorbing fluctuations and complication of memory control circuit, and reducing the cost.

This application is the national phase under 35 U.S.C. § 371 of PCTInternational Application No. PCT/JP00/06955 which has an Internationalfiling date of Oct. 5, 2000, which designated the United States ofAmerica and was not published in English.

TECHNICAL FIELD

The present invention relates to a cell disassembly device such as CLAD(cell assembly and disassembly device) which can transmit and receiveeffective data (effective time slot) on STM (synchronous transfer mode)circuit having plural time slots (TS) divided and multiplexed in time inframe period through ATM (asynchronous transfer mode) network, by using,for example, SDT (structured data transfer) method designated inRecommendation I.363.1 B-ISDN ATM Adaptation Layer Specification: Type 1AAL of ITU-T (Telecommunication Standardization Sector of InternationalTelecommunication Union), a cell disassembly method, and acomputer-readable recording medium recording a program for executingthis method on a computer. More particularly, this invention relates toa cell disassembly device for absorbing fluctuations of cells by abuffer, a cell disassembly method, and a computer-readable recordingmedium recording a program for executing this method on a computer.

BACKGROUND ART

Recently, the ATM communication is noticed as a new communication methodfor the multimedia age. In the conventional STM communication method,during communication, the physical circuit of the STM network is alwaysoccupied in every media between terminals, but in the ATM communicationsystem, the circuit between terminals is set as a logic virtual path,and the physical circuit is occupied dynamically only by the necessaryportion depending on the necessity, so that an efficient multimediacommunication is realized.

FIG. 26 shows a configuration of a system for transmitting and receivingdata on the STM circuit through the ATM network by using a conventionalcell assembly and disassembly device (cell disassembly device).Reference numerals 61 a, 61 b, and 61 c denote conventional cellassembly and disassembly devices which can transmit and receive theeffective data on the STM circuit by transforming into ATM cells(hereinafter called cells), reference numeral 63 denotes an ATM networkfor communication in asynchronous transfer mode, 62 a, 62 b, and 62 cdenote STM circuit interfaces, reference numerals 64 a, 64 b, and 64 cdenote ATM circuit interfaces, and reference numerals 65 a and 65 bdenote virtual paths set on the ATM network 63.

In the STM/ATM communication system having such configuration, effectivedata (continuous data) for the STM circuit interface 62 b entered in thecell assembly and disassembly device 61 a from the STM circuit interface62 a is sequentially assembled into a cell, which is a 53-byte fixedlength packet, in the cell assembly and disassembly device 61 a, and isprovided with VPI (virtual path identifier) #1 in the header, and istransmitted to the ATM network 63 at a specific speed. Consequently, thecell transferred on the virtual path 65 a according to VPI#1 is receivedin the cell assembly and disassembly device 61 b, and is returned fromthe cell into the original continuous data herein, and is transmitted tothe STM circuit interface 62 b.

Similarly, as a flow in reverse direction, effective data for the STMcircuit interface 62 a entered in the cell assembly and disassemblydevice 61 b from the STM circuit interface 62 b is sequentiallyassembled into a cell in the cell assembly and disassembly device 61 b,and is provided with VPI#1 in the header, and is transmitted to the ATMnetwork 63 at a specific speed. Consequently, the cell transferred onthe virtual path 65 a according to VPI#1 is received in the cellassembly and disassembly device 61 a, and is returned into the originalcontinuous data herein, and is transmitted to the STM circuit interface62 a.

On the other hand, effective data (continuous data) for the STM circuitinterface 62 c entered in the cell assembly and disassembly device 61 afrom the STM circuit interface 62 a is sequentially assembled into acell in the cell assembly and disassembly device 61 a, and is providedwith VPI#2 in the header, and is transmitted to the ATM network 63 at aspecific speed. Consequently, the cell transferred on the virtual path65 b according to VPI#2 is received in the cell assembly and disassemblydevice 61 c, and is returned from the cell into the original continuousdata herein, and is transmitted to the STM circuit interface 62 c.

Similarly, as a flow in reverse direction, effective data for the STMcircuit interface 62 a entered in the cell assembly and disassemblydevice 61 c from the STM circuit interface 62 c is sequentiallyassembled into a cell in the cell assembly and disassembly device 61 c,and is provided with VpI#2 in the header, and is transmitted to the ATMnetwork 63 at a specific speed. Consequently, the cell transferred onthe virtual path 65 b according to VPI#2 is received in the cellassembly and disassembly device 61 a, and is returned into the originalcontinuous data herein, and is transmitted to the STM circuit interface62 a.

The cell assembly and disassembly device 61 (cell assembly anddisassembly device 61 a, 61 b, or 61 c) has a structure as shown in afunctional block diagram in FIG. 27. The cell assembly and disassemblydevice 61 comprises the ATM circuit interface unit 71 for terminatingthe ATM circuit interface (physical layer processing), the cell assemblyunit 73 for forming the continuous data received from STM circuitinterface unit 72 into a cell, the cell disassembly unit 74 ford isassembling the cell received from the ATM circuit interface unit 71 torestore into continuous data, the STM circuit interface 72 forterminating the STM circuit interface, and the device management unit 75for managing the entire devices of the cell assembly and disassemblydevice 61. The ATM circuit interface 64 may be any one of the ATMcircuit interfaces 64 a, 64 b, and 64 c, and the STM circuit interface62 may be any one of the STM circuit interfaces 62 a, 62 b, and 62 c.

According to the ITU-T, in the ITU-T Recommendation I.363.1, thestructured data transfer method is designated as the cell transfermethod of data on the STM circuit having a specific frame period throughthe ATM network 63. A cell format used in the conventional structureddata transfer method is shown in FIG. 21. The cell assembly unit 73divides only the effective data extracted from arbitrary plural timeslots, out of the STM circuit interface 62 composed of [64 kb/s]×n (n:natural number) time slots (TS), in the unit of 46 bytes (in the case ofP format) or 47 bytes (in the case of non-P format), adds AAL1 (ATMadaptation layer type 1) header and ATM header (including VPI),assembles the cell in the format shown in FIG. 28 by destination(virtual path 65), and transmits to the ATM circuit interface unit 71.The virtual path 65 is either virtual path 65 a or virtual path 65 b.

On the other hand, the cell disassembly unit 74 analyzes the VPI in theheader of the cell received from the ATM circuit interface unit 71,judges the sender (virtual path 65), analyzes the sequence number in theAAL1 header, detects cell discarding and insertion of wrong cell, andprocesses countermeasures, absorbs delay fluctuations occurring duringcell transfer in the ATM network 63 in every virtual path 65,distributes the data extracted from the payload into necessary timeslots according to the sender, and transmits to the STM circuitinterface unit 72. Further, the cell disassembly unit 74, when receivinga cell in P format, analyzes the pointer field, detects the boundary offrame period in the STM circuit, and determines assignment of which byteof the data extracted from the payload in which time slot.

The cell disassembly unit 74 has a structure as shown in a functionalblock diagram in FIG. 29. The cell disassembly unit 74 comprisesfollowing units. The AAL1 processor 81 for extracting the VPI and data(including frame boundary information) from the received cell, andtransmitting respectively to a write controller 83 and the fluctuationabsorption buffer unit 82. The fluctuation absorption buffer unit 82 fortemporarily storing the data extracted from the payload of the receivedcell together with the frame boundary information directly in everyvirtual path 65 (VPI), and absorbing the delay fluctuation occurringduring cell transfer in the ATM network 63. The write controller 83 foranalyzing the received VPI, judging the sender (virtual path 65), andgenerating a write signal to the fluctuation absorption buffer unit 82on the basis thereof. The buffer monitor unit 84 for monitoring the dataaccumulated amount in the fluctuation absorption buffer unit 82 in everyvirtual path 65 (VPI), and controlling the operation of the writecontroller 83 and read controller 85 on the basis thereof. The readcontroller 85 for reading out the data from the fluctuation absorptionbuffer unit 82 according to the timing information from the STM circuitinterface unit 72 and distributing into necessary time slots. The VP/TSconversion table 86 for storing the corresponding relation of thevirtual path 65 and distribution time slots, and noticing to the readcontroller 85.

The fluctuation absorption buffer 82 has a structure as shown in afunctional block diagram in FIG. 30. The fluctuation absorption buffer82 comprises following units. The separator 91 for distributing thewrite data and frame boundary information from the AAL1 processor 81into individual buffers VPB1 (VPI#1) to VPBm (VPI#m) in a cell buffer 92according to the instruction (write signal) from the write controller83. The cell buffer 92 for storing the write data and frame boundaryinformation temporarily in each virtual path 65 (VPI). The multiplexer93 for multiplexing the data and frame boundary information being redout from the individual buffer VPB1 to VPBm in the cell buffer 92according to the instruction (read signal) from the read controller 85.VPTH1 to VPTHm are the reading-start thresholds set respectively in thebuffer VPB1 to VPBm. Although VPTH1 to VPTHm are shown in FIG. 30, theywill utilized in the explanation of operation provided later. Thesethresholds are actually stored in the buffer monitor unit 84.

The device management unit 75 shown in FIG. 27 manages the entirestructure of the cell assembly and disassembly device 61, and setsnecessary parameters and collects status in the individual units of thecell disassembly unit 74, ATM circuit interface unit 71, cell assemblyunit 73, and STM circuit interface unit 72. To realize this function,the device management unit 75 and individual units are connected througha control bus. For the sake of simplicity of the functional blockdiagram, the control bus is show in FIG. 27 only, but for setting ofparameters and collection of status, sub-blocks in individual unitsshown in FIG. 27, for example, sub-blocks in the cell disassembly unit74 are also connected with control bus.

Further, the data bus width in the ATM circuit interface unit 64 and STMcircuit interface unit 62 is serial (1 bit), but in the cell assemblyand disassembly device 61, generally, data is exchanged in the width of8 bits. For example, when the ATM interface speed is 155.52 MHz, insidethe cell assembly and disassembly device 61, as mentioned above, theinterface is 8-bit wide, and most of the parts operate in the clock ofthe ATM interface system, and therefore the internal basic clock is19.44 MHz (=155.52 MHz/8 bits).

The operation of the conventional cell assembly and disassembly device61 will now be explained. The STM circuit interface 72 shown in FIG. 27converts the bit row received from the STM circuit interface 62 fromserial to parallel (8 bits), extracts the frame boundary and time slot,and transmits all data, together with the timing information, to thecell assembly unit 73. The cell assembly unit 73 assembles only theeffective data in a cell of a format shown in FIG. 28 in everydestination (virtual path 65) according to the instruction (to assignthe data from which time slot into which virtual path 65) from a TS/VPconversion table not shown in the diagram, and transmits to the ATMcircuit interface unit 71. The ATM circuit interface unit 71 inserts thecell received from the cell assembly unit 73 into the payload ofphysical layer frame such as SDH (synchronous digital hierarchy) orSONET (synchronous optical network), converts from parallel to serial,and transmits to the ATM circuit interface 64.

Similarly, as a flow in reverse direction, the ATM circuit interfaceunit 71 converts the bit row received from the ATM circuit interface 64from serial to parallel, processes the physical layer by detecting cellsynchronism or the like, and transmits all effective extracted cellstogether with timing information to the cell disassembly unit 74.

The AAL1 processor 81 in the cell disassembly unit 74 shown in FIG. 29extracts the VPI from the header of the received cell, notices it to thewrite controller 83, and analyzes the sequence number in the AAL1header, and detects cell discarding and insertion of wrong cell. Whencell discarding is detected, in this case, the lost data is compensated(inserting all-1 pattern of 46 bytes if the discarded cell is supposedto be P format, or 47 bytes in the case of non-P format), and furtherwhen the discarded cell is supposed to be P format, the frame boundaryinformation is also predicted and compensated. When a wrong cellinsertion is detected, the wrong inserted cell is discarded. Later, theinformation extracted from the payload of the received cell and frameboundary information are transmitted to the fluctuation absorptionbuffer unit 82.

The write controller 83 analyzes the VPI received from the AAL1processor 81, judges the sender (virtual path 65), generates acorresponding write signal, and transmits to the fluctuation absorptionbuffer unit 82 and buffer monitor unit 84. In FIG. 30, the fluctuationabsorption buffer unit 82 stores, according to the write signal receivedfrom the write controller 83, the data and frame boundary informationreceived from the AAL1 processor 81 temporarily in the individualbuffers VPB1 to VPBm prepared in each virtual path 65 (VPI#1 to #m).

The buffer monitor unit 84 monitors the data accumulated amount held inthe cell buffer 92 in every individual buffers VPB1 to VPBm, from thewrite signal from the write controller 83 and read signal from the readcontroller 85, and controls the operation of the write controller 83 andread controller 85 according to the result. For example, the dataaccumulating amount in the individual buffers VPB1 to VPBm which areempty upon start of communication gradually increases by turning on thewrite action instruction and turning off the read action instructionuntil reaching the reading-start thresholds VPTH1 to VPTHm by writeaction, and when the data accumulated amount reaches the reading-startthresholds VPTH1 to VPTHm, the read action instruction is also turned onsequentially.

The read controller 85, when the reading-start instruction from thebuffer monitor unit 84 is ON, generates read signals to be distributedcorrectly into the time slots in which read data is distributed, andtransmits to the fluctuation absorption buffer unit 82, according to theinstruction (to assign the data from which virtual path 65 into whichtime slot time slot) from the VP/TS conversion table 86, frame boundaryinformation from the fluctuation absorption buffer 82, and timinginformation from the STM circuit interface unit 72.

The VP/TS conversion table 86 stores the corresponding relation of thevirtual path 65 (VPI) and time slot, that is, the information showingwhich virtual path 65 is set (which VPI is present), and which time slotis used by each virtual path 65, and notices the information to the readcontroller 85. The STM circuit interface unit 72 inserts the data beingreadout by the read controller 85 into the payload (time slot) of thephysical layer frame, converts from parallel into serial, and transmitsto the STM circuit interface 62.

Thus, in the conventional method, the received data and frame boundaryinformation are once held in the cell buffer 92 in the fluctuationabsorption buffer 82, and by stopping the reading action (delaying thereading-start timing) until the data accumulated amount reaches thereading-start threshold after start of communication, delay fluctuationsoccurring during cell transfer in the ATM network 63 is absorbed, andthe continuity of the data issued to the STM circuit interface 62 isassured.

Herein, the reading-start thresholds VPTH1 to VPTHm of individualbuffers VPB1 to VPBm can be basically expressed with the followingequation (1), supposing the maximum of the delay fluctuation determinedas the characteristic of the ATM network 63 to be ±D and thecommunication speed of the virtual path 65 accommodated to be V(identifier k=1 to m).VPTHk=Vk×D  (1)

The capacity Lk (identifier k=1 to m) required as individual buffersVPB1 to VPBm can be basically expressed with the following equation (2).Lk=2×VPTHk=2XVk×D  (2)

However, since the received data is written into the cell buffer 82 incell unit, if the calculation result in equation 1 is 47 bytes (worth 1cell) or less, it is general to express as follows.VPTHk=48 bytes (1 cell+1 byte)  (3)Lk=94 bytes (2 cells)  (4)

As shown in equation (2), the capacity L (capacity L1 to Lm) ofindividual buffers VPB1 to VPBm used as fluctuation absorption buffersbasically depends on the communication speed of the virtual bufferaccommodated. Accordingly, in the conventional cell assembly anddisassembly device 61, the cell buffer 92 is realized mainly by thefollowing two methods, that is, the individual memory method and commonmemory method.

In the individual memory method, one memory is divided into plural fixedbanks, and the banks are used as individual buffers VPB1 to VPBm, orplural individual memories are prepared physically, and used asindividual buffers VPB1 to VPBm.

In this method, since the individual buffers VPB1 to VPBm are composedof simple first-in first-out (FIFO) memories, the memory control circuitis simple. However, so as to be flexibly applicable to completelydifferent communication speeds in individual virtual paths 65,capacities of all individual buffers VPB1 to VPBm must conform to themaximum communication speed of the STM circuit interface 62, forexample, in the case of the ISDN (integrated services digital network)temporary group speed interface, the capacity must be large enough toaccommodate the speed of 1.536 Mb/s, and this is the simplestconfiguration and the memory control circuit is the easiest, but thetotal memory capacity becomes extremely large.

Accordingly, it has been attempted to curtail the total memory capacityby providing the applicable communication speed with limiting conditionsand making use of the regularity of the communication speeds in thelimiting conditions. For example, in the limiting conditions “to beapplicable to maximum speed and communication speed to the power of 2 of64 kb/s only,” the memory capacity of individual buffers VPB1 to VPBm iscomposed of 1 for 1.536 Mb/s+2 for 512 kb/s+3 for 256 kb/s+6 for 128kb/s+12 for 64 kb/s. In spite of such curtailing means, however, thecell buffer 92 cannot be realized at the minimum memory cost in thismethod. Features of this method are briefly summarized as follows.

Merit: Memory control circuit is simple.

Demerit: Total memory capacity is very large.

On the other hand, in the common memory method, one memory is finelydivided into cell levels (for example, in the units of 64 bytes each),and obtained memory blocks are commonly shared by all virtual paths 65,and in each virtual path 65 as required, plural memory blocks areoccupied sequentially, and combined in chain, so that the individualbuffers VPB1 to VPBm are realized.

This method is flexibly applicable to various communication speeds, andrequires only a minimum limit of total memory capacity because thememory is shared, but the demerit is that the memory control circuit isvery complicated as disclosed, for example, in Japanese Laid-open PatentNo. 8-331149. The total memory capacity (common memory capacity) Lsrequired in this method may be basically expressed with the followingequation (5), supposing the maximum communication speed of the STMcircuit interface 62 to be Vmax.Ls=2×Vmax×D  (5)

Features of this method are briefly summarized as follows.

Merit: Total memory capacity is small.

Demerit: Memory control circuit is extremely complicated.

According to the prior art, however, since fluctuations are absorbed bythe buffer of which capacity depends on the virtual path which isvariable in communication speed, if attempted to curtail the totalcapacity of the memory for absorbing fluctuations, the memory controlcircuit is complicated and the cost is increased, or if attempted tosimplify the memory control circuit, the total capacity of the memoryfor absorbing fluctuations becomes large, and the cost is increased,too.

It is an object of this invention to provide a cell disassembly devicecapable of suppressing both increase of total capacity of cell forabsorbing fluctuations and complication of memory control circuit. It isalso an object of this invention to provide a cell disassembly methodand a computer-readable recording medium which records a computerprogram that realizes the method according to this invention on acomputer.

DISCLOSURE OF THE INVENTION

The cell disassembly device according to this invention comprises a celldisassembly unit which disassembles a cell received from an ATM circuitinterface, extracts data from payload, distributing data in plural timeslots divided and multiplexed in time in frame period according to asender (virtual path), and sends out to an STM circuit interface; and abuffer provided in each time slot, wherein the cell disassembly unitstores the data distributed in each time slot temporarily in the buffer,and absorbs fluctuations of the cell.

According to the above-mentioned cell disassembly device, the celldisassembly unit stores the data distributed in each time slottemporarily in the buffer provided in each time slot, and absorbsfluctuations of the cell. Therefore, fluctuations can be absorbed ineach time slot constant in communication speed, and the capacity of eachbuffer is always enough at the minimum capacity (the capacity enough toaccommodate communication speed in each time slot) regardless of thecommunication speed of virtual path, and the memory is composed in asimple structure.

In the cell disassembly device according to another aspect of thisinvention, the cell disassembly unit accumulates data after start ofcommunication by writing data distributed in each time slot into thebuffer, reads out the data from the buffer, parallel to writing, whenthe data accumulated amount in the buffer reaches a prescribed amount,and sends out the read data to the STM circuit interface.

According to the above-mentioned cell disassembly device, the celldisassembly unit accumulates data after start of communication bywriting data distributed in each time slot into the buffer, reads outthe data from the buffer, parallel to writing, when the data accumulatedamount in the buffer reaches a prescribed amount, and sends out the readdata to the STM circuit interface. Therefore, fluctuations can beabsorbed in a simple procedure.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit accumulates data after start ofcommunication by writing data distributed in each time slot into thebuffer, reads out the data from the buffer, parallel to writing, whenpassing a first prescribed time, and sends out the read data to the STMcircuit interface.

According to the above-mentioned cell disassembly device, the celldisassembly unit accumulates data after start of communication bywriting data distributed in each time slot into the buffer, reads outthe data from the buffer, parallel to writing, when passing a firstprescribed amount, and sends out the read data to the STM circuitinterface. Therefore, fluctuations can be absorbed in a simpleprocedure.

The cell disassembly device according to still another aspect of thisinvention further comprises a setting unit which sets the prescribedamount or first prescribed time.

According to the above-mentioned cell disassembly device, the prescribedamount or first prescribed time can be set by the setting unit.Therefore, the prescribed amount or first prescribed time can beadjusted depending on the environments of use.

The cell disassembly device according to still another aspect of thisinvention further comprises a measuring unit which measures fluctuationsof the cell, in which the setting unit sets the value of the prescribedamount or first prescribed time on the basis of the result ofmeasurement by the measuring unit.

According to the above-mentioned cell disassembly device, the measuringunit measures fluctuations of the cell, and the setting unit sets thevalue of the prescribed amount or first prescribed time on the basis ofthe result of measurement by the measuring unit. Therefore, theprescribed amount or first prescribed time can be adjusted automaticallyand appropriately.

In the cell disassembly device according to still another aspect of thisinvention, the prescribed amount or first prescribed time is presentindependently in each buffer, and the cell disassembly unit determinesthe reading-start timing from the buffer independently in each buffer.

According to the above-mentioned cell disassembly device, the prescribedamount or first prescribed time is present independently in each buffer,and the cell disassembly unit determines the reading-start timing fromthe buffer independently in each buffer, and therefore the reading-starttiming can be controlled finely in each buffer.

In the cell disassembly device according to still another aspect of thisinvention, the prescribed amount or first prescribed time is presentindependently in each virtual path, and the cell disassembly unitdetermines the reading-start timing from the buffer independently inevery one or two or more buffers corresponding to each virtual path.

According to the above-mentioned cell disassembly device, the prescribedamount or first prescribed time is present independently in each virtualpath, and the cell disassembly unit determines the reading-start timingfrom the buffer independently in every one or two or more bufferscorresponding to each virtual path, and therefore it is higher inprobability that the data to be issued in a same frame is actuallyissued in the same frame.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit starts reading action from allbuffers corresponding to the virtual path when the data accumulatedamount reaches the prescribed amount or passing the prescribed firsttime from start of communication, in more than a specified number ofbuffers out of one or two or more buffers corresponding to a samevirtual path.

According to the above-mentioned cell disassembly device, the celldisassembly unit starts reading action from all buffers corresponding tothe virtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in more than a specified number, for example, one or more of buffers outof one or two or more buffers corresponding to a same virtual path.Therefore, in a simple method, the reading-start timing in every one ortwo or more buffers corresponding to each virtual path can becontrolled.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit starts reading action from allbuffers corresponding to the virtual path when the data accumulatedamount reaches the prescribed amount or passing the prescribed firsttime from start of communication, in all buffers out of one or two ormore buffers corresponding to a same virtual path.

According to the above-mentioned cell disassembly device, the celldisassembly unit starts reading action from all buffers corresponding tothe virtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in all buffers out of one or two or more buffers corresponding to a samevirtual path, and therefore, in a simple method, the reading-starttiming in every one or two or more buffers corresponding to each virtualpath can be controlled.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit once stops, when an underflowoccurs in the buffer, reading out from the buffer having the underflow,and resumes reading out when the data accumulated amount reaches againthe prescribed amount or passing a second prescribed time afteroccurrence of underflow.

According to the above-mentioned cell disassembly device, the celldisassembly unit once stops, when an underflow occurs in the buffer,reading out from the buffer having the underflow, and resumes readingout when the data accumulated amount reaches again the prescribed amountor passing a second prescribed time after occurrence of underflow, andtherefore if an underflow occurs, a normal communication can berecovered promptly.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit, when an underflow occurs in anyone of one or two or more buffers corresponding to a same virtual path,resets all buffers corresponding to this virtual path, and once stopswriting and reading in these buffers, and resumes writing so that thedata belonging to a same frame period may be accumulated uniformly atthe beginning of these buffers, and resumes reading out when the dataaccumulated amount in these buffers reaches again the prescribed amountor passing a second prescribed time after execution of resetting.

According to the above-mentioned cell disassembly device, the celldisassembly unit, when an underflow occurs in any one of one or two ormore buffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anunderflow occurs, a normal communication can be recovered promptly.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit resets, when an overflow occurs inthe buffer, the buffer having the overflow, once stops reading out fromthis buffer, and resumes reading out when the data accumulated amountreaches again the prescribed amount or passing a second prescribed timeafter execution of resetting.

According to the above-mentioned cell disassembly device, the celldisassembly unit resets, when an overflow occurs in the buffer, thebuffer having the overflow, once stops reading out from this buffer, andresumes reading out when the data accumulated amount reaches again theprescribed amount or passing a second prescribed time after execution ofresetting, and therefore if an overflow occurs, a normal communicationcan be recovered promptly.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit, when an overflow occurs in any oneof one or two or more buffers corresponding to a same virtual path,resets all buffers corresponding to this virtual path, and once stopswriting and reading in these buffers, and resumes writing so that thedata belonging to a same frame period may be accumulated uniformly atthe beginning of these buffers, and resumes reading out when the dataaccumulated amount in these buffers reaches again the prescribed amountor passing a second prescribed time after execution of resetting.

According to the above-mentioned cell disassembly device, the celldisassembly unit, when an overflow occurs in any one of one or two ormore buffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anoverflow occurs, a normal communication can be recovered promptly.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit once stops, when an overflow occursin the buffer, writing into the buffer having the overflow, and resumeswriting when the data accumulated amount in this buffer decreases to theprescribed amount or passing a second prescribed time after occurrenceof overflow.

According to the above-mentioned cell disassembly device, the celldisassembly unit once stops, when an overflow occurs in the buffer,writing into the buffer having the overflow, and resumes writing whenthe data accumulated amount in this buffer decreases to the prescribedamount or passing a second prescribed time after occurrence of overflow,and therefore if an overflow occurs, a normal communication can berecovered promptly.

In the cell disassembly device according to still another aspect of thisinvention, the cell disassembly unit, when an overflow occurs in any oneof one or two or more buffers corresponding to a same virtual path, oncestops writing in all buffers corresponding to this virtual path, andresumes writing when the data accumulated amount in these buffersdecreases again to the prescribed amount or passing a second prescribedtime after occurrence of overflow.

According to the above-mentioned cell disassembly device, the celldisassembly unit once stops, when an overflow occurs in the buffer,writing into the buffer having the overflow, and resumes writing whenthe data accumulated amount in this buffer decreases to the prescribedamount or passing a second prescribed time after occurrence of overflow,and therefore if an overflow occurs, a normal communication can berecovered promptly, and therefore if an overflow occurs, a normalcommunication can be recovered promptly.

The cell disassembly device according to still another aspect of thisinvention further comprises an increasing or extending unit whichincreases the prescribed amount or extends the second prescribed timewhen an underflow occurs in the buffer.

According to the above-mentioned is cell disassembly device, theincreasing or extending unit increases the prescribed amount or extendsthe second prescribed time when an underflow occurs in the buffer.Therefore, recurrence of underflow can be automatically decreased.

The cell disassembly device according to still another aspect of thisinvention further comprises an increasing or extending unit whichincreases the prescribed amount or extends the second prescribed timewhen an overflow occurs in the buffer.

According to the above-mentioned cell disassembly device, the increasingor extending unit increases the prescribed amount or extends the secondprescribed time when an overflow occurs in the buffer. Therefore,recurrence of underflow can be automatically decreased.

The cell disassembly method according to still another aspect of thisinvention is a cell disassembly method for disassembling a cell receivedfrom an ATM circuit interface, extracting data from payload,distributing data in plural time slots divided and multiplexed in timein frame period according to a sender (virtual path), and sending out toan STM circuit interface, comprising the step of storing the datadistributed in each time slot temporarily in a buffer provided in eachtime slot, and absorbing fluctuations of the cell.

According to the above-mentioned cell disassembly method, the storingstep stores the data distributed in each time slot temporarily in thebuffer provided in each time slot, and absorbs fluctuations of the cell.Therefore, fluctuations can be absorbed in each time slot constant incommunication speed, and the capacity of each buffer is always enough atthe minimum capacity (the capacity enough to accommodate communicationspeed in each time slot) regardless of the communication speed ofvirtual path, and the memory is composed in a simple structure.

In the cell disassembly method according to still another aspect of thisinvention, the storing step comprises a step of accumulating data afterstart of communication by writing data distributed in each time slotinto the buffer, a step of reading out the data from the buffer,parallel to writing, when the data accumulated amount in the buffer atthe accumulating step reaches a prescribed amount, and a step of sendingout the read data to the STM circuit interface.

According to the above-mentioned cell disassembly method, theaccumulating step accumulates data after start of communication bywriting data distributed in each time slot into the buffer, the readingand writing step reads out the data from the buffer, parallel towriting, when the data accumulated amount in the buffer at theaccumulating step reaches a prescribed amount, and the sending stepsends out the read data to the STM circuit interface. Therefore,fluctuations can be absorbed in a simple procedure.

In the cell disassembly method according to still another aspect of thisinvention, the storing step comprises a step of accumulating data afterstart of communication by writing data distributed in each time slotinto the buffer, a step of reading out the data from the buffer,parallel to writing, when data is accumulated at the accumulating stepfor a first prescribed time, and a step of sending out the read data tothe STM circuit interface.

According to the above-mentioned cell disassembly method, theaccumulating step accumulates data after start of communication bywriting data distributed in each time slot into the buffer, the readingand writing step reads out the data from the buffer, parallel towriting, when the data is accumulated at the accumulating step for afirst prescribed amount, and the sending step sends out the read data tothe STM circuit interface. Therefore, fluctuations can be absorbed in asimple procedure.

The cell disassembly method according to still another aspect of thisinvention further comprises a step of setting the prescribed amount orfirst prescribed time.

According to the above-mentioned cell disassembly method, the prescribedamount or first prescribed time can be set at the setting step.Therefore, the prescribed amount or first prescribed time can beadjusted depending on the environments of use.

The cell disassembly method according to still another aspect of thisinvention further comprises a step of measuring fluctuations of thecell, in which the setting step sets the value of the prescribed amountor first prescribed time on the basis of the result of measurement atthe measuring step.

According to the above-mentioned cell disassembly method, the measuringstep measures fluctuations of the cell, and the setting step sets thevalue of the prescribed amount or first prescribed time on the basis ofthe result of measurement at the measuring step. Therefore, theprescribed amount or first prescribed time can be adjusted automaticallyand appropriately.

In the cell disassembly method according to still another aspect of thisinvention, the prescribed amount or first prescribed time is presentindependently in each buffer, and the reading and writing stepdetermines the reading-start timing from the buffer independently ineach buffer.

According to the above-mentioned cell disassembly method, the prescribedamount or first prescribed time is present independently in each buffer,and the reading and writing step determines the reading-start timingfrom the buffer independently in each buffer, and therefore thereading-start timing can be controlled finely in each buffer.

In the cell disassembly method according to still another aspect of thisinvention, the prescribed amount or first prescribed time is presentindependently in each virtual path, and the reading and writing stepdetermines the reading-start timing from the buffer independently inevery one or two or more buffers corresponding to each virtual path.

According to the above-mentioned cell disassembly method, the prescribedamount or first prescribed time is present independently in each virtualpath, and the reading and writing step determines the reading-starttiming from the buffer independently in every one or two or more bufferscorresponding to each virtual path, and therefore it is higher inprobability that the data to be issued in a same frame is actuallyissued in the same frame.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step starts reading action from allbuffers corresponding to the virtual path when the data accumulatedamount reaches the prescribed amount or passing the prescribed firsttime from start of communication, in more than a specified number ofbuffers out of one or two or more buffers corresponding to a samevirtual path.

According to the above-mentioned cell disassembly method, the readingand writing step starts reading action from all buffers corresponding tothe virtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in more than a specified number, for example, one or more of buffers outof one or two or more buffers corresponding to a same virtual path.Therefore, in a simple method, the reading-start timing in every one ortwo or more buffers corresponding to each virtual path can becontrolled.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step starts reading action from allbuffers corresponding to the virtual path when the data accumulatedamount reaches the prescribed amount or passing the prescribed firsttime from start of communication, in all buffers out of one or two ormore buffers corresponding to a same virtual path.

According to the above-mentioned cell disassembly method, the readingand writing step starts reading action from all buffers corresponding tothe virtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in all buffers out of one or two or more buffers corresponding to a samevirtual path, and therefore, in a simple method, the reading-starttiming in every one or two or more buffers corresponding to each virtualpath can be controlled.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step once stops, when an underflowoccurs in the buffer, reading out from the buffer having the underflow,and resumes reading out when the data accumulated amount reaches againthe prescribed amount or passing a second prescribed time afteroccurrence of underflow.

According to the above-mentioned cell disassembly method, the readingand writing step once stops, when an underflow occurs in the buffer,reading out from the buffer having the underflow, and resumes readingout when the data accumulated amount reaches again the prescribed amountor passing a second prescribed time after occurrence of underflow, andtherefore if an underflow occurs, a normal communication can berecovered promptly.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step, when an underflow occurs in anyone of one or two or more buffers corresponding to a same virtual path,resets all buffers corresponding to this virtual path, and once stopswriting and reading in these buffers, and resumes writing so that thedata belonging to a same frame period may be accumulated uniformly atthe beginning of these buffers, and resumes reading out when the dataaccumulated amount in these buffers reaches again the prescribed amountor passing a second prescribed time after execution of resetting.

According to the above-mentioned cell disassembly method, the readingand writing step, when an underflow occurs in any one of one or two ormore buffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anunderflow occurs, a normal communication can be recovered promptly.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step resets, when an overflow occursin the buffer, the buffer having the overflow, once stops reading outfrom this buffer, and resumes reading out when the data accumulatedamount reaches again the prescribed amount or passing a secondprescribed time after execution of resetting.

According to the above-mentioned cell disassembly method, the readingand writing step resets, when an overflow occurs in the buffer, thebuffer having the overflow, once stops reading out from this buffer, andresumes reading out when the data accumulated amount reaches again theprescribed amount or passing a second prescribed time after execution ofresetting, and therefore if an overflow occurs, a normal communicationcan be recovered promptly.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step, when an overflow occurs in anyone of one or two or more buffers corresponding to a same virtual path,resets all buffers corresponding to this virtual path, and once stopswriting and reading in these buffers, and resumes writing so that thedata belonging to a same frame period may be accumulated uniformly atthe beginning of these buffers, and resumes reading out when the dataaccumulated amount in these buffers reaches again the prescribed amountor passing a second prescribed time after execution of resetting.

According to the above-mentioned cell disassembly method, the readingand writing step, when an overflow occurs in any one of one or two ormore buffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anoverflow occurs, a normal communication can be recovered promptly.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step once stops, when an overflowoccurs in the buffer, writing into the buffer having the overflow, andresumes writing when the data accumulated amount in this bufferdecreases to the prescribed amount or passing a second prescribed timeafter occurrence of overflow.

According to the above-mentioned cell disassembly method, the readingand writing step once stops, when an overflow occurs in the buffer,writing into the buffer having the overflow, and resumes writing whenthe data accumulated amount in this buffer decreases to the prescribedamount or passing a second prescribed time after occurrence of overflow,and therefore if an overflow occurs, a normal communication can berecovered promptly.

In the cell disassembly method according to still another aspect of thisinvention, the reading and writing step, when an overflow occurs in anyone of one or two or more buffers corresponding to a same virtual path,once stops writing in all buffers corresponding to this virtual path,and resumes writing when the data accumulated amount in these buffersdecreases again to the prescribed amount or passing a second prescribedtime after occurrence of overflow.

According to the above-mentioned cell disassembly method, the readingand writing step once stops, when an overflow occurs in the buffer,writing into the buffer having the overflow, and resumes writing whenthe data accumulated amount in this buffer decreases to the prescribedamount or passing a second prescribed time after occurrence of overflow,and therefore if an overflow occurs, a normal communication can berecovered promptly, and therefore if an overflow occurs, a normalcommunication can be recovered promptly.

The cell disassembly method according to still another aspect of thisinvention further comprises an increasing or extending step ofincreasing the prescribed amount or extending the second prescribed timewhen an underflow occurs in the buffer.

According to the above-mentioned cell disassembly method, the increasingor extending step increases the prescribed amount or extends the secondprescribed time when an underflow occurs in the buffer. Therefore,recurrence of underflow can be automatically decreased.

The cell disassembly method according to still another aspect of thisinvention further comprises an increasing or extending step ofincreasing the prescribed amount or extending the second prescribed timewhen an overflow occurs in the buffer.

According to the above-mentioned cell disassembly method, the increasingor extending step increases the prescribed amount or extends the secondprescribed time when an overflow occurs in the buffer. Therefore,recurrence of overflow can be automatically decreased.

In the cell disassembly method according to still another aspect of thisinvention, the second prescribed time is a first prescribed time.

According to the above-mentioned cell disassembly method, a sameprescribed time can be defined for the first prescribed time and secondprescribed time. Therefore, in the event of overflow or underflow, whenthe second prescribed time is extended, the first prescribed time isalso extended.

The computer-readable recording medium according to still another aspectof this invention stores a computer program that causes a computer toexecute the method according to this invention.

According to the above-mentioned computer-readable recording medium,since the method of the invention can be executed by the computer, bothincrease of total capacity of the memory for absorbing fluctuations andcomplication of memory control circuit can be suppressed, so that thecost can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a system for transmitting andreceiving data on STM circuit through ATM network by means of a cellassembly and disassembly device in a first embodiment of the invention;

FIG. 2 is a functional block diagram showing a configuration of the cellassembly and disassembly device in the first embodiment of theinvention;

FIG. 3 is a functional block diagram showing a configuration of celldisassembly unit in the first embodiment shown in FIG. 2;

FIG. 4 is a functional block diagram showing a configuration offluctuation absorption buffer unit in the first embodiment shown in FIG.3;

FIG. 5 is a flowchart showing flow of fluctuation absorption process inthe first embodiment;

FIG. 6 is a flowchart showing flow of underflow process in the firstembodiment;

FIG. 7 is a flowchart showing flow of overflow process in the firstembodiment;

FIG. 8 is a flowchart showing other flow of overflow process in thefirst embodiment;

FIG. 9 is a functional block diagram showing a configuration of celldisassembly unit in a second embodiment of the invention;

FIG. 10 is a flowchart showing flow of fluctuation absorption process inthe second embodiment;

FIG. 11 is a flowchart showing flow of underflow process in the secondembodiment;

FIG. 12 is a flowchart showing flow of overflow process in the secondembodiment;

FIG. 13 is a flowchart showing other flow of overflow process in thesecond embodiment;

FIG. 14 is a functional block diagram showing a configuration of celldisassembly unit in a third embodiment of the invention;

FIG. 15 is an explanatory diagram showing a method of determiningreading-start timing in the third embodiment;

FIG. 16 is an explanatory diagram showing other method of determiningreading-start timing in the third embodiment;

FIG. 17 is a flowchart showing flow of fluctuation absorption process inthe third embodiment;

FIG. 18 is a flowchart showing flow of underflow process in the thirdembodiment;

FIG. 19 is a flowchart showing flow of overflow process in the thirdembodiment;

FIG. 20 is a flowchart showing other flow of overflow process in thethird embodiment;

FIG. 21 is a functional block diagram showing a configuration of celldisassembly unit in a fourth embodiment of the invention;

FIG. 22 is a flowchart showing flow of fluctuation absorption process inthe fourth embodiment;

FIG. 23 is a flowchart showing flow of underflow process in the fourthembodiment;

FIG. 24 is a flowchart showing flow of overflow process in the fourthembodiment;

FIG. 25 is a flowchart showing other flow of overflow process in thefourth embodiment;

FIG. 26 is a functional block diagram showing a system for transmittingand receiving data on STM circuit through ATM network by means of a cellassembly and disassembly device in a prior art;

FIG. 27 is a functional block diagram showing a configuration of theconventional cell assembly and disassembly device shown in FIG. 26;

FIG. 28 is an explanatory diagram showing a cell format used in aconventional structured data transfer method;

FIG. 29 is a functional block diagram showing a configuration of aconventional cell disassembly unit shown in FIG. 27; and

FIG. 30 is a functional block diagram showing a configuration offluctuation absorption buffer shown in FIG. 29.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to the drawings, preferred embodiments of a celldisassembly device, a cell disassembly method, and a computer-readablerecording medium recording a program for executing this method by acomputer according to the invention are described specifically below. Itmust be noted, however, that the invention is not limited to theseembodiments alone.

A cell disassembly device in the first embodiment is a cell assembly anddisassembly device comprising buffers provided in each time slot forstoring data distributed in each time slot temporarily, and absorbingdelay fluctuations occurring in cell transfer in ATM network,multiplexing fluctuations occurring in cell transfer, and other cellfluctuations (sometimes merely called fluctuations hereafter).

FIG. 1 is a block diagram showing a system for transmitting andreceiving data on STM circuit through ATM network by means of a cellassembly and disassembly device in the first embodiment of theinvention. Same parts as in FIG. 26 are identified with same referencenumerals, and their explanation is omitted. In the system shown in FIG.1, instead of the conventional cell assembly and disassembly devices 61a, 61 b, and 61 c shown in FIG. 26, cell assembly and disassemblydevices 1 a, 1 b, and 1 c of the first embodiment are disposed.

FIG. 2 is a functional block diagram showing a configuration of the cellassembly and disassembly device 1 (cell assembly and disassembly device1 a, 1 b, or 1 c) in the first embodiment of the invention. Same partsas in FIG. 27 are identified with same reference numerals, and theirexplanation is omitted. The cell assembly and disassembly device 1 has acell disassembly unit 2 of the first embodiment instead of the celldisassembly unit 74 of the conventional cell assembly and disassemblydevice 61.

FIG. 3 is a functional block diagram showing a configuration of the celldisassembly unit 2 in the first embodiment shown in FIG. 2. The celldisassembly unit 2 comprises an AAL1 processor 12 for extracting theVPI, frame boundary information and data from the received cell, andtransmitting the VPI and frame boundary information to a writecontroller 13 and data to a fluctuation absorption buffer unit 11, thefluctuation absorption buffer unit 11 for temporarily storing the dataextracted from the payload of the received cell separately in each timeslot (TS), and absorbing the fluctuation, the write controller 13 foranalyzing the received VPI, judging the sender (virtual path 65), andgenerating a write signal to the fluctuation absorption buffer unit 11on the basis the result and frame boundary information, a buffer monitorunit 14 for monitoring the data accumulated amount in the fluctuationabsorption buffer unit 11 in every time slot (TS), and controlling theoperation of the write controller 13, read controller 15, andfluctuation absorption buffer unit 11 on the basis the result and thereading-start threshold from a reading-start threshold setting unit 16,the read controller 15 for reading out the data from the fluctuationabsorption buffer unit 11 according to the timing information from theSTM circuit interface unit 72 and distributing into necessary timeslots, the reading-start threshold setting unit 16 for noticing thereading-start threshold used in control of the timing for startingreading (reading-start timing) from a buffer 22 described below to thebuffer monitor unit 14, and a VP/TS conversion table 17 for storing thecorresponding relation of the virtual path 65 and distribution timeslots, and noticing to the write controller 13 and read controller 15.

The fluctuation absorption buffer unit 11 is provided as a sub-block inthe cell disassembly unit 2 same as in the prior art. The configurationand cell format of the cell assembly and disassembly device 1 are sameas the configuration and cell format of the conventional cell assemblyand disassembly device 61 shown in FIG. 27 and FIG. 28, except that theinternal structure of the absorption fluctuation buffer unit 11 ismainly different.

FIG. 4 is a functional block diagram showing a configuration of thefluctuation absorption buffer unit 11 in the first embodiment shown inFIG. 3. The fluctuation absorption buffer unit 11 has individual buffersB1 (TS#1) to Bn (TS#n) (buffers of the invention) provided in each timeslot, and comprises a time slot buffer 22 for storing write datatemporarily in each time slot individually, a separator 21 fordistributing write data from the AAL1 processor 12 into individualbuffers B1 to Bn in the time slot buffer 22 according to an instruction(write signal) from the write controller 13, and a multiplexer 23 formultiplexing the data being read out from the individual buffers B1 toBn in the time slot buffer 22 according to an instruction (read signal)from the read controller 15. In FIG. 4, TH1 to THn are reading-startthresholds set in the individual buffers B1 to Bn. For the sake ofexplanation, TH1 to THn are shown in FIG. 4, but actually these valuesare held in the reading-start threshold setting unit 16.

In the cell assembly and disassembly device 1, an ATM circuit interfaceunit 71 converts the bit row received from the ATM circuit interface 64from serial to parallel, and processes the physical layer by detectingcell synchronism or the like, and transmits all extracted effectivecells to the cell disassembly unit 2 together with the timinginformation. The AAL1 processor 12 in the cell disassembly unit 2extracts the VPI from the header of the received cell, notices to thewrite controller 13, and analyzes the sequence number in the AAL1header, and detects cell discarding and insertion of wrong cell.

When cell discarding is detected, in this case, the lost data iscompensated (inserting all-1 pattern of 46 bytes if the discarded cellis supposed to be P format, or 47 bytes in the case of non-P format),and further when the discarded cell is supposed to be P format, theframe boundary information is also predicted and compensated. When awrong cell insertion is detected, the wrong inserted cell is discarded.Later, the information extracted from the payload of the received cellis transmitted to the fluctuation absorption buffer unit 11, and theframe boundary information is transmitted to the write controller 13.

The write controller 13 analyzes the VPI received from the AAL1processor 12, judges the sender (virtual path 65), determines the on/offtiming of the write signal provided in each time slot from the result ofthis judgment, the VP (virtual path 65)/TS (time slot) conversioninformation received from the VP/TS conversion table 17 and the frameboundary information received from the AAL1 processor 12, generates awrite signal according to the result of decision, and transmits to thefluctuation absorption buffer unit 11 and buffer monitor unit 14. Thefluctuation absorption buffer unit 11 stores, according to the writesignal received from the write controller 13, the data received from theAAL1 processor 12 temporarily in the individual buffers B1 to Bnprepared in each time slot (TS#1 to TS#n) by dividing and distributingin time slot units.

The buffer monitor unit 14 monitors the data accumulated amount held inthe time slot buffer 22 in every individual buffers B1 to Bn, from thewrite signal from the write controller 13 and read signal from the readcontroller 15, and controls the operation of the write controller 13 andread controller 15 according to the result of monitoring. For example,the data accumulating amount in the individual buffers B1 to Bn whichare empty upon start of communication gradually increases by turning onthe write action instruction and turning off the read action instructionuntil reaching the reading-start thresholds TH1 to THn by write action,and when the data accumulated amount reaches the reading-startthresholds, the read action instruction is also turned on sequentially.

If an underflow or an overflow is detected in the individual buffers B1to Bn, it is noticed to the reading-start threshold setting unit 16. Anunderflow is a state of individual buffers B1 to Bn becoming empty, notallowing to read out any longer, and an overflow is a state of theaccumulated amount exceeding a specified threshold. This specificthreshold is, for example, 2 times as much as the reading-startthreshold, and the reading-start thresholds TH1 to THn should not bemore than half of the capacity of the individual buffers B1 to Bn.

The read controller 15, when the reading-start instruction from thebuffer monitor unit 14 is ON, generates read signals to be distributedcorrectly into the time slots in which read data is distributed,according to the instructions from the VP/TS conversion table 17(showing which time slot is effective or which individual buffer isbeing used) and the timing information from the STM circuit interfaceunit 72, and transmits to the fluctuation absorption buffer unit 11. Thereading-start threshold setting unit 16 stores the reading-startthresholds TH1 to THn for individual buffers B1 to Bn in the time slotbuffer 22, and notices them to the buffer monitor unit 14. Whenreceiving notice of occurrence of overflow or underflow from the buffermonitor unit 14, the reading-start threshold is changed.

The VP/TS conversion table 17 stores the corresponding relation of thevirtual path 65 (VPI) and time slot, that is, the information showingwhich virtual path 65 is set (which VPI is present), and which time slotis used by each virtual path 65, and notices the information (VP/TSconversion information) to the write controller 13 and read controller15. The STM circuit interface unit 72 inserts the data being read out bythe read controller 15 into the payload (time slot) of the physicallayer frame, converts from parallel into serial, and transmits to theSTM circuit interface 62.

The reading-start thresholds TH1 to THn are independently held in thereading-start threshold setting unit 16. The reading-start timing fromthe individual buffers B1 to Bn in the time slot buffer 22 is determinedindependently in the individual buffers B1 to Bn by the buffer monitorunit 14. Setting or change of reading-start thresholds TH1 to THn heldin the reading-start threshold setting unit 16 may be operated by theuser or manager by means of DIP switch not shown in the diagram, or froma device managing unit 75 through control bus not shown, or by using anoriginal setting panel.

In this constitution, the operation of the first embodiment is explainedbelow by referring to the flowchart in FIG. 5 to FIG. 8. The same partsas in the prior art mentioned above are not explained, and only thecharacteristic parts of the invention different from the prior art, thatis, steps of absorbing fluctuations (fluctuation absorption process)conducted in the cell disassembly unit 2 are explained below. FIG. 5 isa flowchart showing flow of fluctuation absorption process in the firstembodiment. In the fluctuation absorption process in the firstembodiment, first of all, reading-start thresholds TH1 to THn are set inthe reading-start threshold setting unit 16 (step S1).

When communication is started, the buffer monitor unit 14 controls thewrite controller 13, and starts to write the data distributed in eachtime slot into the corresponding individual buffers B1 to Bn in the timeslot buffer 22, and repeats writing only until the data accumulatedamount in the individual buffers B1 to Bn reaches the correspondingreading-start thresholds TH1 to THn (steps S2, S3). When the amount ofdata accumulated in any one of the individual buffers reaches thereading-start threshold corresponding to the individual buffer, the readcontroller 15 is controlled, and in this individual buffer, reading isstarted parallel to writing (step S4). This writing and reading processis executed in a simple first-in first-out (FIFO) principle.

In succession, checking for occurrence of underflow or overflow (stepsS5, S6), steps S4 to S6 are repeated until underflow or overflow takesplace. Herein, the read controller 15 reads out at a specific intervalin each time slot, and fluctuations are absorbed. In the event of anunderflow, the underflow process mentioned below is executed (step S7),and the process returns to step S4. In the event of an overflow, theoverflow process mentioned below is executed (step S8), and the processreturns to step S4.

In FIG. 5, for the sake of explanation, step S1 is placed at thebeginning of the flowchart, but setting of reading-start thresholds TH1to THn at step S1 is not required again if once set in the pastcommunication. In the midst of communication, the reading-startthresholds TH1 to THn may be changed (set again). As a result, thereading-start thresholds TH1 to THn can be changed depending on theenvironments.

It is a major feature of the first embodiment that fluctuations areabsorbed in each time slot, not in each virtual path 65. Whatever may bethe maximum communication speed of the STM circuit interface 62 (forexample, whether ISDN primary group speed or secondary group speed), thecommunication speed in each time slot is always 64 kb/s, and thereading-start thresholds TH1 to THn of individual buffers B1 to Bn ineach time slot and necessary capacity L are basically expressed asfollows, same as in the foregoing equations 1 and 2, supposing themaximum of the delay fluctuation determined as the characteristic of theATM network 63 to be ±D (identifier k=1 to n).THk=[64 kb/s]×D  (6)Lk=2×THk=2×[64 kb/s]×D  (7)

However, if only one time slot is assigned for one virtual path 65,since the received data is written into the time slot buffer 22 in cellunit, in order to cope with such a case, if the calculation result inequation 6 is 47 bytes (worth 1 cell) or less, it is necessary toexpress as follows same as in the foregoing equations 3 and 4.THk=48 bytes(1 cell+1 byte)  (8)Lk=94 bytes(2 cells)  (9)

As clear from equations 6 to 9, THk and Lk are always constant, notdepending on the identifier k.

Besides, as shown below, the total memory capacity Lt of the time slotbuffer 22 is basically same as the total memory capacity Ls of the cellbuffer 92 in the common memory method of the prior art.

$\begin{matrix}{\begin{matrix}{{Lt} = {{\sum\;{Lk}} = {2 \times \lbrack {64\mspace{14mu}{kb}\text{/}s} \rbrack \times n \times D}}} \\{= {{2 \times V\;\max \times D} = {Ls}}}\end{matrix}\quad} & (10)\end{matrix}$

Further, in the STM circuit interface 62, by controlling so that thedata to be issued in the same frame may be written in the mutually sameconfiguration (to be read in the same frame) in the individual buffersB1 to Bn, the internal composition of the time slot buffer 22 itself isthe frame boundary information, and it is not necessary to store theframe boundary information separately in the memory as in theconventional method. As a result, the total memory capacity may befurther decreased from that of the conventional common memory method. Inthis case, to read out from the time slot buffer 22, it is as simple asto read out sequentially from the individual buffer B1 to Bn in the sameframe, and the control circuit in the read controller 15 is alsosimplified.

As known from the explanation so far, since the capacity L of theindividual buffers B1 to Bn does not depend on the communication speedof the virtual path 65, same as in the conventional individual memorysystem, the individual buffers B1 to Bn can be composed of simplefirst-in first-out (FIFO) memories, and the capacity L is alwayssufficient at minimum capacity (capacity enough to accommodatecommunication speed of 64 kb/s), and therefore the memory controlcircuit in the fluctuation absorption buffer 11 is simpler than in theconventional individual memory system. In addition to delayfluctuations, it may be also designed to determine the memory quantityof the time slot buffer 22 in consideration of multiplexing fluctuationsoccurring in cell transfer and others.

The underflow processing at step S7 is explained below. FIG. 6 is aflowchart showing flow of underflow process in the first embodiment. Inthe underflow processing in the first embodiment, the buffer monitorunit 14 detecting occurrence of an underflow in any one of theindividual buffers B1 to Bn once turns off the read action instructionto the read controller 15, and temporarily stops reading out from theindividual buffer having the underflow (step S26). Consequently, thereading-start threshold corresponding to the individual buffer havingthe underflow is increased by a specified amount (step S27). Insuccession, until the data accumulated amount in this individual bufferreaches again the reading-start threshold corresponding to thisindividual buffer, only writing is repeated in this individual buffer(steps S28, S29). When the data accumulated amount in this individualbuffer reaches again the reading-start threshold corresponding to thisindividual buffer, reading from this individual buffer is resumed (stepS30).

Thus, in the underflow processing in the first embodiment, reading fromthe individual buffer having the underflow is once stopped, and when thedata accumulated amount later reaches the reading-start thresholdcorresponding to this individual buffer again, reading is resumed. Thatis, when an underflow occurs, the operation is same as the operationright after start of communication. Besides, the reading-start thresholdcorresponding to the individual buffer having the underflow isautomatically increased by a specified amount. That is, upon everyoccurrence of underflow, the fixed delay added to the data isautomatically increased by a specific amount each.

Therefore, if an underflow occurs, a normal communication state isrecovered promptly, and the fixed delay added to the data forfluctuation absorption can be automatically increased as required. Thereading-start thresholds TH1 to THn should not exceed the half value ofthe capacity of the individual buffers B1 to Bn. Fluctuations arecomposed of those in the delaying direction and others in advancingdirection, which are considered to occur at same probability, andtherefore if the reading-start thresholds TH1 to THn exceed the halfvalue of the capacity of the individual buffers B1 to Bn, the data mayoverflow from the individual buffers B1 to Bn.

The overflow processing at step S8 is explained. FIG. 7 is a flowchartshowing flow of overflow process in the first embodiment. In theoverflow processing in the first embodiment, the buffer monitor unit 14detecting occurrence of an overflow in any one of the individual buffersB1 to Bn first transmits a reset instruction to the individual bufferhaving the overflow to the fluctuation absorption buffer 11, and resetsthis individual buffer. Once turning off the read action instruction tothe read controller 15, reading out from the individual buffer havingthe overflow is stopped temporarily (step S46).

Consequently, the reading-start threshold corresponding to theindividual buffer having the overflow is increased by a specified amount(step S47). In succession, until the data accumulated amount in thisindividual buffer reaches again the reading-start thresholdcorresponding to this individual buffer, only writing is repeated inthis individual buffer (steps S48, S49). When the data accumulatedamount in this individual buffer reaches again the reading-startthreshold corresponding to this individual buffer, reading from thisindividual buffer is resumed (step S50).

Thus, in the overflow processing in the first embodiment, the individualbuffer having the overflow is reset, and reading from this individualbuffer is once stopped, and when the data accumulated amount laterreaches the reading-start threshold corresponding to this individualbuffer again, reading is resumed. That is, when an overflow occurs, theoperation is same as the operation right after start of communication.Besides, the reading-start threshold corresponding to the individualbuffer having the overflow is automatically increased by a specifiedamount. That is, upon every occurrence of overflow, the fixed delayadded to the data is automatically increased by a specific amount each.

FIG. 8 is a flowchart showing other flow of overflow process in thefirst embodiment. In the overflow processing, the buffer monitor unit 14detecting occurrence of an overflow in any one of the individual buffersB1 to Bn once turns off the write action instruction to the writecontroller 13, and temporarily stops writing into the individual bufferhaving the overflow (step S66). Consequently, the reading-startthreshold corresponding to the individual buffer having the overflow isincreased by a specified amount (step S67). In succession, until thedata accumulated amount in this individual buffer decreases again to thereading-start threshold corresponding to this individual buffer, onlyreading is repeated in this individual buffer (steps S68, S69). When thedata accumulated amount in this individual buffer decreases again to thereading-start threshold corresponding to this individual buffer, writingis resumed (step S70).

Thus, in this overflow processing, writing into the individual bufferhaving the overflow is once stopped, and when the data accumulatedamount decreases to the reading-start threshold corresponding to thisindividual buffer again, writing is resumed. That is, when an overflowoccurs, the write operation and read operation are opposite to theoperation at the time of underflow (writing and reading being exchangedmutually). Besides, the reading-start threshold corresponding to theindividual buffer having the overflow is automatically increased by aspecified amount. That is, upon every occurrence of overflow, the fixeddelay added to the data is automatically increased by a specific amounteach.

By these overflow processes, if an overflow occurs, a normalcommunication state is recovered promptly, and the fixed delay added tothe data for fluctuation absorption can be automatically increased asrequired. Further, if the threshold for overflow detection is set at 2times the reading-start thresholds TH1 to THn, along with elevation ofthe reading-start thresholds TH1 to THn, the threshold for overflowdetection climbs up, and the probability of occurrence of overflowdecreases.

Same as in the occurrence of underflow, the reading-start thresholds TH1to THn should not exceed the half value of the capacity of theindividual buffers B1 to Bn. Fluctuations are composed of those in thedelaying direction and others in advancing direction, which areconsidered to occur at same probability, and therefore if thereading-start thresholds TH1 to THn exceed the half value of thecapacity of the individual buffers B1 to Bn, the data may overflow fromthe individual buffers B1 to Bn.

As described herein, according to the first embodiment, sincefluctuations are absorbed in each time slot, instead of each virtualpath 65, after distributing data into time slots, increase of totalmemory capacity and complication of memory control circuit can besuppressed. In other words, both decrease of total memory capacity andsimplification of memory control circuit can be realized at the sametime. In the event of an underflow, reading from the individual bufferhaving the underflow is once stopped, and when the data accumulatedamount later reaches again the reading-start threshold corresponding tothis individual buffer, reading is resumed, so that a normalcommunication state is recovered promptly in a simple procedure in theevent of an underflow.

Similarly, in the event of an overflow, the individual buffer having theoverflow is reset, and reading from this individual buffer is oncestopped, and when the data accumulated amount later reaches again thereading-start threshold corresponding to this individual buffer, readingis resumed, or writing into the individual buffer having the overflow isonce stopped, and when the data accumulated amount later decreases againto the reading-start threshold corresponding to this individual buffer,writing is resumed, and therefore a normal communication state isrecovered promptly in a simple procedure in the event of an overflow.

Moreover, on every occurrence of underflow or overflow, the fixed delayadded to the data is automatically increased by a specific amount each,and the fixed delay added to the data for fluctuation absorption can beincreased automatically as required. Further, the reading-startthreshold used initially upon start of communication and thereading-start threshold used after occurrence of underflow or overflowmay be different from each other, but when they are set as the samereading-start thresholds TH1 to THn, the change of reading-startthreshold upon occurrence of underflow or overflow may be also reflectedupon start of communication.

In the first embodiment, the reading-start timing from the time slotbuffer 22 is “when the buffer monitor unit 14 detects for the first timethat the data accumulated amount in the individual buffers B1 to Bnreaches the reading-start thresholds TH1 to THn,” but in the secondembodiment, by contrast, it is the time “when the buffer monitor unit 14detects the lapse of time after start of communication reaches thereading-start wait time W1 to Wn.” That is, in the first embodiment, thedata accumulated mount is the trigger of reading start, whereas in thesecond embodiment, the lapse of time after start of communication is thetrigger of reading start.

The second embodiment is basically same as the first embodiment inconfiguration, and explanation is omitted in same parts, and onlydifferent parts are explained below. FIG. 9 is a functional blockdiagram showing a configuration of cell disassembly unit in the secondembodiment of the invention. Same parts as in FIG. 3 are identified withsame reference numerals. The cell disassembly unit 31 in the secondembodiment comprises a buffer monitor unit 32 and a reading-start waittime setting unit 33, instead of the buffer monitor unit 2 andreading-start threshold setting unit 16 in the cell disassembly unit 2in the first embodiment.

The reading-start wait time setting unit 33 is similar to thereading-start threshold setting unit 16 in the first embodiment inconfiguration and operation, but differs that it stores reading-startwait times W1 to Wn for individual buffers B1 to Bn in the time slotbuffer 22, instead of red start thresholds TH1 to THn, and that itnotices them to the buffer monitor unit 32. Setting or change ofreading-start wait times W1 to Wn in the reading-start wait time settingunit 33 may be operated by the user or manager by means of DIP switchnot shown in the diagram, or from a device managing unit 75 throughcontrol bus not shown, or by using an original setting panel.

The buffer monitor unit 32 is same as the buffer monitor unit 14 in thefirst embodiment in configuration, but is slightly different inoperation. The buffer monitor unit 32 monitors the write signal from thewrite controller 13 in every individual buffers B1 to Bn, and controlsthe reading-start timing according to the result. For example, bymonitoring the write signal, the communication start timing of each oneof individual buffers B1 to Bn is detected, and when communication isstarted, internal timers T1 to Tn, not shown, provided in individualbuffers B1 to Bn are operated, and the lapse of time after start ofcommunication is measured.

The result of measurement of lapse of time and reading-start wait timesW1 to W2 from the reading-start wait time setting unit 33 are compared,and the write operation instruction is turned on and the read operationinstruction is turned off until the lapse of time reaches thereading-start wait times W1 to Wn, and the read operation instruction isalso turned on to start reading sequentially from the one reaching thelapse of time of W1 to Wn. If an underflow or overflow is detected inthe individual buffers B1 to Bn, it is noticed to the reading-start waittime setting unit 33. Receiving this notice, the reading-start wait timesetting unit 33 changes the reading-start wait time.

In the second embodiment having such configuration, the operation isexplained below by referring to the flowcharts in FIG. 10 to FIG. 13. Inthe second embodiment, the operation is same as in the first embodiment,and explanation is omitted as for same parts, and only different partsare explained. FIG. 10 is a flowchart showing flow of fluctuationabsorption process in the second embodiment. Same pars as in FIG. 5 areidentified with same reference numerals. In the fluctuation absorptionprocess in the second embodiment, instead of setting of reading-startthresholds TH1 to THn at step S1, the reading-start wait times W1 to Wnis set (step S11). Further, instead of judging whether the dataaccumulated amount in the individual buffers B1 to Bn has reached thereading-start thresholds TH1 to THn or not at step S3, it is judgedwhether passing the reading-start wait times W1 to Wn or not at stepS12.

That is, once communication is started, the buffer monitor unit 32controls the write controller 13, starts the process of writing datadistributed into time slots into individual corresponding buffers B1 toBn in the time slot buffer 22, and repeats writing only until the lapseof time from start of communication of the individual buffers W1 to Wnreaches the corresponding reading-start wait times W1 to Wn (steps S2,S12). When the lapse of time from start of communication of any one ofthe individual buffers reaches the reading-start wait time correspondingto the individual buffer, the read controller 15 is controlled, andwriting and reading are started simultaneously in this individual buffer(step S4) Instead of the underflow processing at step S7 and overflowprocessing at step S8, the underflow processing at step S13 and overflowprocessing at step S14 mentioned below are executed. In FIG. 10, for thesake of explanation, step S11 is placed at the beginning of theflowchart, but setting of reading-start wait times W1 to Wn at step S11is not required again if once set in the past communication. In themidst of communication, the reading-start wait times W1 to Wn may bechanged (set again). As a result, the reading-start wait times W1 to Wncan be changed depending on the environments.

The underflow processing at step S13 is explained below. FIG. 11 is aflowchart showing flow of underflow process in the second embodiment.Same parts as in FIG. 6 are identified with same reference numerals. Inthe underflow processing in the second embodiment, instead of increasingthe reading-start threshold by a specified amount at step S27, thereading-start wait time is extended by a specified time at step S31.Further, instead of judging if the data accumulated amount in theindividual buffer having the underflow has reached the reading-startthreshold again at step S29, it is judged at step S32, after occurrenceof underflow, if passing over the reading-start wait time correspondingto the individual buffer having the underflow.

That is, the buffer monitor unit 32 detecting occurrence of underflow atindividual buffers B1 to Bn once turns off the read operationinstruction corresponding to the read controller 15, and once stopsreading from the individual buffer having the underflow (step S26), andextends the reading-start wait time for the individual buffer having theunderflow by a specified time (step S31). Until the time of lapse afteroccurrence of underflow reaches the reading-start wait timecorresponding to this individual buffer, only writing is done in thisindividual buffer (steps S28, S32), and then reading is resumed (stepS30).

The overflow processing at step S14 is explained below. FIG. 12 is aflowchart showing flow of overflow process in the second embodiment.Same parts as in FIG. 7 are identified with same reference numerals. Inthe overflow processing in the second embodiment, instead of increasingthe reading-start threshold by a specified amount at step S47, thereading-start wait time is extended by a specified time at step S51.Further, instead of judging if the data accumulated amount in theindividual buffer having the underflow has reached the reading-startthreshold again at step S49, it is judged at step S52, after resettingat step S46, if passing over the reading-start wait time correspondingto the individual buffer having the overflow.

That is, the buffer monitor unit 32 detecting occurrence of overflow atindividual buffers B1 to Bn transmits a resetting instruction for theindividual buffer having the overflow to the fluctuation absorptionbuffer 1 to reset this individual buffer, and once turns off the readoperation instruction the read controller 15, and stop temporarilyreading from the individual buffer having the overflow (step S46). Thereading-start wait time corresponding to the individual buffer havingthe overflow is extended by a specified time (step S51), and until thetime of lapse after execution of resetting reaches the reading-startwait time corresponding to this individual buffer, only writing isrepeated in this individual buffer (steps S48, S52), and then reading isresumed (step S50).

FIG. 13 is a flowchart showing other flow of overflow process in thesecond embodiment. Same parts as in FIG. 8 are identified with samereference numerals. In this overflow processing, instead of increasingthe reading-start threshold at step S67, the reading-start wait time isextended by a specified time at step S71 (in this case, when thereading-start wait time is shortened, the fixed delay added to the datais increased). Further, instead of judging if the data accumulatedamount in the individual buffer having the underflow has decreased tothe reading-start threshold at step S69, it is judged at step S72, afteroccurrence of overflow, if passing over the reading-start wait timecorresponding to this individual buffer.

That is, the buffer monitor unit 32 detecting occurrence of overflow atindividual buffers B1 to Bn once turns off the write operationinstruction to the write controller 13, and stops writing into theindividual buffer having the overflow (step S66), and shortens thereading-start wait time corresponding to the individual buffer havingthe overflow by a specified time (step S71). Until passing over thereading-start wait time corresponding to this individual buffer, onlyreading is repeated in this individual buffer (steps S68, S72), and thenwriting is resumed (step S70).

Thus, according to the second embodiment, upon start of communication orin the event of overflow or underflow, if reading or writing iscontrolled depending on the lapse of time, the same effects as in thefirst embodiment are obtained.

In the first embodiment, the reading-start thresholds TH1 to THn areheld in the reading-start threshold setting unit 16 in each time slot,and the reading-start timing in the buffer monitor unit 14 is controlledin each time slot, but in the third embodiment, it is designed tocontrol in every virtual path 65. That is, the reading-start timing isindependently determined in the individual buffers B1 to Bn in the firstembodiment, whereas in the third embodiment it is designed to determinethe reading-start timing in batch by grouping the individual buffers B1to Bn into those corresponding to one same virtual path 65.

The third embodiment is basically same as the first embodiment inconfiguration, and only different parts are explained. FIG. 14 is afunctional block diagram showing a configuration of cell disassemblyunit in the third embodiment of the invention. Same parts as in FIG. 3are identified with same reference numerals. A cell disassembly unit 41in the third embodiment comprises a buffer monitor unit 42 and areading-start threshold setting unit 43, instead of the buffer monitorunit 14 and reading-start threshold setting unit 16 of the celldisassembly unit 2 in the first embodiment.

The reading-start threshold setting unit 43 is same as the reading-startthreshold setting unit 16 in the first embodiment in configuration andoperation, except that the reading-start thresholds VPTH1 to VPTHm inevery virtual path 65 same as in the prior art are held, instead of thereading-start thresholds TH1 to THn in every time slot, by receivingVP/TS conversion information from the VP/TS conversion table 17, andthey are noticed to the buffer monitor unit 42. Setting or change ofreading-start thresholds VPTH1 to VPTHm in the reading-start thresholdsetting unit 43 may be operated by the user or manager by means of DIPswitch not shown in the diagram, or from a device managing unit 75through control bus not shown, or by using an original setting panel.

The buffer monitor unit 42 is composed same as in the first embodiment,and monitors the write signal from the write controller 13 in individualbuffers B1 to Bn same as in the first embodiment, and determines thereading-start timing on the basis of the result, but those correspondingto a same virtual path 65 are grouped together to be controlled to startreading at the same time. By such control, it is assured more securelythan in the first embodiment that the data to be issued in the sameframe in the STM circuit interface 62 are actually issued in the sameframe. If an underflow or overflow occurs in the individual buffers B1to Bn, it is noticed to the reading-start threshold setting unit 43.Receiving this notice, the reading-start threshold setting unit 43changes the reading-start threshold.

The method of determining the reading-start timing of the groupedindividual buffers B1 to Bn is explained by referring to FIG. 15. FIG.15 is an explanatory diagram in which three individual buffers B1 to B3are grouped together. As shown in the diagram, the data accumulatedamounts in the individual buffers B1 to B3 are not always the same. Itis highly possible that more data is accumulated temporarily in the timeslot of earlier (smaller) number. In the determining method ofreading-start timing in the third embodiment, when the accumulated dataamount in one of the individual buffers in the group reaches thereading-start threshold VPTH1 corresponding to the group, It iscontrolled to start reading from all individual buffers B1 to B3 in thisgroup.

That is, the reading-start timing from the grouped individual buffers B1to Bn is “the moment the buffer monitor unit 42 first detects that thedata accumulated amount in any one of the individual buffers in thegroup reaches the reading-start threshold corresponding to the group.”In other words, the reading-start timing is determined by the “ORcondition” in the group.

FIG. 16 is an explanatory diagram showing other method of determiningreading-start timing in the third embodiment, in which three individualbuffers B1 to B3 are grouped together same as in FIG. 15. As shown inthe diagram, when the data accumulated amount in all individual buffersin the group reaches the reading-start threshold VPTH1, it is controlledto start reading from all of individual buffers B1 to B3 in the group.That is, the reading-start timing is “the moment the buffer monitor unit42 first detects that the data accumulated amount in all of theindividual buffers in the group reaches the reading-start thresholdcorresponding to the group.” In other words, the reading-start timing isdetermined by the “AND condition” in the group.

Further, it may be defined to be “the moment the buffer monitor unit 42first detects that the data accumulated amount in a specified number (anarbitrary number from one to all) of the individual buffers in the groupreaches the reading-start threshold corresponding to the group.” Thus,in the third embodiment, the reading-start timing can be determinedeasily in each virtual path 65, and the cost can be reduced.

The operation of the third embodiment having such configuration isexplained by referring to FIG. 17 to FIG. 20. Same parts as in the firstembodiment are not explained, and only different parts are explainedbelow. FIG. 17 is a flowchart showing flow of fluctuation absorptionprocess in the third embodiment. Same parts as in FIG. 5 are identifiedwith same reference numerals.

In the fluctuation absorption process in the third embodiment, insteadof setting process of reading-start thresholds TH1 to THn at step S1,reading-start thresholds VPTH1 to VPTHm are set at step S16. Further,instead of judging whether the data accumulated amounts in theindividual buffers B1 to Bn have reached the reading-start thresholdsTH1 to THn or not at step S3, it is judged in each group whether thedata accumulated amount in at least one individual buffer in the grouphas reaches the corresponding reading-start threshold or not at stepS17. At step S17, meanwhile, it may be also judged in each group whetherthe data accumulated amount in all individual buffers in the same grouphas reached the respective corresponding reading-start threshold or not.

When communication is started, the buffer monitor unit 42 controls thewrite controller 13, and starts to write the data distributed in eachtime slot into the corresponding individual buffers B1 to Bn in the timeslot buffer 22, and repeats writing only until the data accumulatedamount in at least one individual buffer in the group reaches thecorresponding reading-start threshold in each group (steps S2, S17). Inany group, when the data accumulated amount in at least one individualbuffer reaches the reading-start threshold corresponding to this group,reading of all individual buffers in this group is started (step S4).

Instead of the underflow process S7 and overflow process S8, theunderflow process S18 and overflow process S19 mentioned below areexecuted. In FIG. 17, for the sake of explanation, step S16 is placed atthe beginning of the flowchart, but setting of reading-start thresholdsVPTH1 to VPTHm at step S1 is not required again if once set in the pastcommunication. In the midst of communication, the reading-startthresholds VPTH1 to VPTHm may be changed (set again). As a result, thereading-start thresholds VPTH1 to VPTHm can be changed depending on theenvironments.

The underflow process at step S18 is explained. FIG. 18 is a flowchartshowing flow of underflow process in the third embodiment. In theunderflow processing in the third embodiment, the buffer monitor unit 42detecting occurrence of underflow in the individual buffers B1 to Bnfirst transmits the reset instruction for the individual buffers B1 toBn having the underflow and all individual buffers (of a same group)corresponding to a same virtual path 65, to the fluctuation absorptionbuffer 11, and resets these individual buffers. The write operationinstruction to the write controller 13 and read operation instruction tothe read controller 15 are once turned off, and processing of writingand reading in these individual buffers is once stopped (step S35).

The reading-start threshold corresponding to this virtual path 65(corresponding to this group) is increased by a specified amount (stepS36). Writing is started by turning on the write operation instructionto the write controller 13 so that the data belonging to a same frameperiod may be accumulated uniformly at the beginning of these individualbuffers (step S37). In this group, consequently, only writing isrepeated in these individual buffers until the data accumulated amountin at least one individual buffer reaches again the reading-startthreshold corresponding to this group (steps S38, S39). Herein, in thisgroup, only writing may be repeated in these individual buffers untilthe data accumulated amount in all individual buffers reaches again thereading-start threshold corresponding to this group. Afterwards, in thisgroup, when the data accumulated amount in at least one individualbuffer reaches again the reading-start threshold corresponding to thisgroup, reading of all individual buffers in this group is resumed (stepS40).

Thus, if an underflow occurs in any one of the individual buffers (of asame group) corresponding to a same virtual path 65, all individualbuffers corresponding to this virtual path 65 are reset, and writing andreading are stopped once, and then writing is started so that the databelonging to the same frame period may be accumulated uniformly at thebeginning of these individual buffers, and further when the dataaccumulated amount in one or all of the individual buffers in this groupreaches the reading-start threshold corresponding to this group, readingof all individual buffers in the group is resumed.

That is, in the underflow processing, after resetting all individualbuffers corresponding to the same virtual path 65, the same operation asthe operation right after start of communication is done. Besides, thereading-start threshold corresponding to the group having the underflowis automatically increased by a specified amount. That is, upon everyoccurrence of underflow, the fixed delay added to the data isautomatically increased by a specific amount each.

Therefore, if an underflow occurs, a normal communication state isrecovered promptly, and the fixed delay added to the data forfluctuation absorption can be automatically increased as required. Thereading-start thresholds VPTH1 to VPTHm should not exceed the half valueof the capacity of the individual buffers B1 to Bn. Fluctuations arecomposed of those in the delaying direction and others in advancingdirection, which are considered to occur at same probability, andtherefore if the reading-start thresholds VPTH1 to VPTHm exceed the halfvalue of the capacity of the individual buffers B1 to Bn, the data mayoverflow from the individual buffers B1 to Bn.

The overflow process at step S19 is explained. FIG. 19 is a flowchartshowing flow of overflow process in the third embodiment. In theoverflow processing in the third embodiment, the buffer monitor unit 42detecting occurrence of overflow in the individual buffers B1 to Bnfirst transmits the reset instruction for the individual buffer havingthe overflow and all individual buffers corresponding to a same virtualpath 65, to the fluctuation absorption buffer 11, and resets theseindividual buffers. The write operation instruction to the writecontroller 13 and read operation instruction to the read controller 15are once turned off, and processing of writing and reading in theseindividual buffers is once stopped (step S55).

The reading-start threshold corresponding to this virtual path 65 isincreased by a specified amount (step S56). Writing is resumed byturning on the write operation instruction to the write controller 13 sothat the data belonging to a same frame period may be accumulateduniformly at the beginning of these individual buffers B1 to Bn (stepS57). In this group, consequently, only writing is executed in theseindividual buffers until the data accumulated amount in at least oneindividual buffer reaches again the reading-start thresholdcorresponding to this group (steps S58, S59).

Herein, in this group, only writing may be executed in these individualbuffers until the data accumulated amount in all individual buffersreaches again the reading-start threshold corresponding to this group.Afterwards, in this group, when the data accumulated amount in at leastone individual buffer reaches again the reading-start thresholdcorresponding to this group, reading of all individual buffers in thisgroup is resumed (step S60).

Thus, if an overflow occurs in any one of the individual buffers (of asame group) corresponding to a same virtual path 65, all individualbuffers corresponding to this virtual path 65 are reset, and writing andreading are stopped once, and then writing is started so that the databelonging to the same frame period may be accumulated uniformly at thebeginning of these individual buffers, and further when the dataaccumulated amount in one or all of the individual buffers in this groupreaches the reading-start threshold corresponding to this group, readingof all individual buffers in the group is resumed. Besides, thereading-start threshold corresponding to the group having the overflowis automatically increased by a specified amount. That is, upon everyoccurrence of underflow, the fixed delay added to the data isautomatically increased by a specific amount each.

FIG. 20 is a flowchart showing other flow of overflow process in thethird embodiment. In this overflow processing, the buffer monitor unit42 detecting occurrence of overflow in the individual buffers B1 to Bnfirst stops writing turning off the write instruction once to the writecontroller 13, for the individual buffer having the overflow and allindividual buffers (of a same group) corresponding to a same virtualpath 65 (step S76). Then the reading-start threshold corresponding tothis virtual path 65 is increased (step S77).

In this group, consequently, until the data accumulated amount in atleast one individual buffer decreases again to the reading-startthreshold corresponding to this group, only reading is executed in theseindividual buffers (steps S78, S79). Herein, in this group, only readingmay be executed in these individual buffers until the data accumulatedamount in all individual buffers decreases again to the reading-startthreshold corresponding to this group. Afterwards, in this group, whenthe data accumulated amount in at least one individual buffer decreasesagain to the reading-start threshold corresponding to this group,writing of all individual buffers in this group is resumed (step S80).

Thus, if an overflow occurs in any one of the individual bufferscorresponding to a same virtual path 65, writing in all individualbuffers corresponding to this virtual path 65 is once stopped, andwriting is resumed when the data accumulated amount in one or all of theindividual buffers decreases again to the reading-start threshold. Thatis, in the event of an overflow, the write operation and read operationare reverse to the operation in the event of an underflow (mutuallyexchanging the write operation and read operation). Besides, thereading-start threshold corresponding to the group having the overflowis automatically increased by a specified amount. That is, upon everyoccurrence of overflow, the fixed delay added to the data isautomatically increased by a specific amount each.

Therefore, if an overflow occurs, a normal communication state isrecovered promptly, and the fixed delay added to the data forfluctuation absorption can be automatically increased as required.Further, if the threshold for overflow detection is set at 2 times ofthe reading-start thresholds VPTH1 to VPTHm, along with the elevation ofreading-start thresholds VPTH1 to VPTHm, the threshold for overflowdetection also climbs up, and the probability of overflow is lowered.The reading-start thresholds VPTH1 to VPTHm should not exceed the halfvalue of the capacity of the individual buffers B1 to Bn. Fluctuationsare composed of those in the delaying direction and others in advancingdirection, which are considered to occur at same probability, andtherefore if the reading-start thresholds VPTH1 to VPTHm exceed the halfvalue of the capacity of the individual buffers B1 to Bn, the data mayoverflow from the individual buffers B1 to Bn.

Thus, according to the third embodiment, the same effects as in thefirst embodiment are obtained, and further those corresponding to a samevirtual path 65 are grouped together and controlled to start reading atthe same time, and it hence heightens the probability that the data tobe issued in the same frame in the STM circuit interface 62 may beactually issued in the same frame.

In the third embodiment, the data accumulated amount is used as thetrigger for starting reading, whereas in the fourth embodiment thetrigger for starting reading is the lapse of time after start ofcommunication. In the first to third embodiments, the value of thereading-start threshold or reading-start wait time held in thereading-start threshold setting unit or reading-start wait time settingunit can be “changed by the instruction of the user or manager of thedevice” by means of DIP switch or setting through a control bus from thedevice managing unit 75, but in the fourth embodiment, the value can be“changed automatically by measuring the maximum value of the delayfluctuations in every virtual path 65.” That is, in the first to thirdembodiments, the values of the reading-start threshold or reading-startwait time is “semifixed,” but it is “set automatically” in the fourthembodiment.

The fourth embodiment is basically same as the third embodiment inconfiguration, and the explanation is omitted in the same parts, andonly different parts are explained. FIG. 21 is a functional blockdiagram showing a configuration of cell disassembly unit in the fourthembodiment of the invention. Same parts as in FIG. 14 are identifiedwith same reference numerals. A cell disassembly unit 51 in the fourthembodiment comprises a buffer monitor unit 52 and a reading-start waittime setting unit 53, in stead of the buffer monitor unit 42 andreading-start threshold setting unit 43 of the cell disassembly unit 41in the third embodiment.

The reading-start wait time setting unit 53 is similar to thereading-start threshold setting unit 43 in the third embodiment inconfiguration and operation, except that reading-start wait times VPW1to VPWm in each virtual path 65 are held instead of the reading-startthresholds VPTH1 to VPTHm, and are noticed to the buffer monitor unit52.

The buffer monitor unit 52 is similar to the buffer monitor unit 42 inthe third embodiment in configuration, but is partly different inoperation. The buffer monitor unit 52 monitors the write signal from thewrite controller 13 in individual buffers B1 to Bn, determines thereading-start timing on the basis of the result, and controls to startreading at the same time by grouping together as for those correspondingto a same virtual path 65. For example, by monitoring the write signal,the communication start timing of each one of individual buffers B1 toBn is detected, and when communication is started, internal timers T1 toTn, not shown, provided in individual buffers B1 to Bn are started tomeasure the lapse of time from start of communication. The result ofmeasurement of lapse of time and reading-start wait times VPW1 to VPWmfrom the reading-start wait time setting unit 53 are compared, and thewrite operation instruction is kept ON and the read operationinstruction is kept OFF until the lapse of time reaches VPW1 to VPWm.

The read operation instruction is turned on simultaneously in allbuffers in the same group. The timing for turning on the read operationinstruction (reading-start timing) may be either the moment the lapse oftime after start of communication reaches the reading-start wait time inany one of the buffers in the group, or the moment the lapse of timeafter start of communication reaches the reading-start wait time in allof the buffers in the group.

The buffer monitor unit 52, after the reading-start timing isdetermined, continues to monitor the data accumulated amount in theindividual buffers B1 to Bn, and notices to the reading-start wait timesetting unit 53. If an underflow or overflow is detected, it is noticedto the reading-start wait time setting unit 53. Receiving the notice ofunderflow or overflow, the reading-start wait time setting unit 53extends the held reading-start wait times VPW1 to VPWm by a specifiedtime.

Setting or changing of reading-start wait times VPW1 to VPWm in thereading-start wait time setting unit 53 may be operated either by theuser or manager by using DIP switch or the like same as in the first tothird embodiments, or by the reading-start wait time setting unit 53 formeasuring the maximum value (effective value D′) of delay fluctuationsin every virtual path 65 for changing automatically on the basis of theresult.

In the latter case, the reading-start wait time setting unit 53 monitorsthe information of data accumulated amount of individual buffers B1 toBn sent from the buffer monitor unit 52, and calculates the effectivevalue D1 of delay fluctuations in every virtual path 65 from the amountof variations. Later, on the basis of the calculated effective amountD1, the reading-start wait times VPW1 to VPWm are changed (optimized) toa minimum value not to induce overflow or underflow. As a result, thefixed delay added to the data for fluctuation absorption in the celldisassembly unit 51 can be automatically suppressed to a minimum limit,and appropriate communication is realized.

After the read operation from the time slot buffer 22 has been started,however, if the values of the reading-start wait times VPW1 to VPWm arechanged according to the same procedure, there is basically no effect onthe operation of the cell disassembly unit 51. Accordingly, theoptimized value is applied actually only when the same virtual path 65is set again after the virtual path 65 is once disconnected, or when anoverflow or underflow occurs. Or, in order that the optimized value maybe applied instantly, the fluctuation absorption buffer unit 11 may beonce reset by force.

In the fourth embodiment having such configuration, the operation isexplained by referring to the flowcharts in FIG. 22 to FIG. 25. Sameparts as in the first embodiment are not explained, and only differentparts are explained herein. FIG. 22 is a flowchart showing flow offluctuation absorption process in the fourth embodiment. Same parts asin FIG. 17 are identified with same reference numerals.

In the fluctuation absorption process in the fourth embodiment, insteadof the setting process of reading-start thresholds VPTH1 to VPTHm atstep S16, step S21 and step S22 are processed. That is, thereading-start wait time setting unit 53 monitors the information of thedata accumulated amount of individual buffers B1 to Bn transmitted fromthe buffer monitor unit 52, and calculates the effective value D′ ofdelay fluctuations in every virtual path 65 from the amount ofvariations (step S21), and sets the reading-start wait times VPW1 toVPWm on the basis of the calculated effective value D1 (step S22). Thisprocess is repeated parallel to other processes during communication,and the reading-start wait times VPW1 to VPWm are updated from time totime.

At step S17, in each group, instead of judging if the data accumulatedamount in at least one individual buffer in the same group has reachedthe corresponding reading-start threshold or not, it is judged, at stepS23, in each group, if the lapse of time after start of communication inat least one individual buffer in the same group has reached thecorresponding reading-start wait time or not. Or, herein, it may be alsojudged if the lapse of time after start of communication in all ofindividual buffers in the same group has reached the correspondingreading-start wait time or not.

That is, when communication is started, the buffer monitor unit 52controls the write controller 13, and starts to write the datadistributed in each time slot into the corresponding individual buffersB1 to Bn in the time slot buffer 22, and repeats writing only until thelapse of time after start of communication in at least one individualbuffer in the group reaches the corresponding reading-start wait time(steps S2, S23). In any group, when the lapse of time after start ofcommunication in at least one individual buffer reaches thereading-start wait time corresponding to this group, reading of allindividual buffers in this group is started (step S4). Besides, insteadof the underflow process S18 and overflow process S19, the underflowprocess S24 and overflow process S25 mentioned below are executed.

The underflow process at step S24 is explained. FIG. 23 is a flowchartshowing flow of underflow process in the fourth embodiment. Same partsas in FIG. 18 are identified with same reference numerals. In theunderflow processing in the fourth embodiment, instead of the process ofincreasing the reading-start threshold at step S36, the reading-startwait time is extended by a specified time at step S41. Further, insteadof step S39 for judging if the data accumulated amount in at least oneindividual buffer in the group having the underflow has reached thereading-start threshold corresponding to the group or not, it is judgedat step S42 if passing over the reading-start wait time corresponding tothe group having the underflow after executing of resetting at step S35.

That is, after resetting at step S35, the buffer monitor unit 52 extendsthe reading-start wait time corresponding to the group having theunderflow by a specified time (step S41). After exudation of resetting,until passing over the reading-start wait time corresponding to thisgroup, only writing is executed in the individual buffers in this group(steps S38, S42), and then reading is resumed (step S40).

The overflow process at step S25 is explained. FIG. 24 is a flowchartshowing flow of overflow process in the fourth embodiment. Same parts asin FIG. 19 are identified with same reference numerals. In the overflowprocessing in the fourth embodiment, instead of the process ofincreasing the reading-start threshold at step S56, the reading-startwait time is extended by a specified time at step S61. Further, insteadof step S59 for judging if the data accumulated amount in at least oneindividual buffer in the group having the overflow has reached thereading-start threshold corresponding to the group or not, it is judgedat step S62 if passing over the reading-start wait time corresponding tothe group having the overflow after executing of resetting at step S55.

That is, after resetting at step S55, the buffer monitor unit 52 extendsthe reading-start wait time corresponding to the group having theoverflow by a specified time (step S61). After execution of resetting,until passing over the reading-start wait time corresponding to thisgroup, only writing is executed in the individual buffers in this group(steps S58, S62), and then reading is resumed (step S60).

FIG. 25 is a flowchart showing other flow of overflow process in thefourth embodiment. Same parts as in FIG. 20 are identified with samereference numerals. In this overflow processing, instead of the processof increasing the reading-start threshold at step S77, the reading-startwait time is shortened by a specified time at step S81. Further, insteadof step S79 for judging if the data accumulated amount in at least oneindividual buffer in the group having the overflow has reached thereading-start threshold corresponding to the group or not, it is judgedat step S82 if passing over the reading-start wait time corresponding tothe group having the overflow after occurrence of overflow.

That is, after stopping writing at step S76, the buffer monitor unit 52shortens the reading-start wait time corresponding to the group havingthe overflow is extended by a specified time (step S81). Afteroccurrence of overflow, until passing over the reading-start wait timecorresponding to this group, only reading is executed in the individualbuffers in this group (steps S78, S82), and then writing is resumed(step S80).

According to the fourth embodiment, as described herein, same effects asin the third embodiment are obtained, and moreover by measuring theeffective value D′, and changing (optimizing) the reading-start waittimes VPW1 to VPWm so as to be a minimum value not to induce overflow orunderflow according to the result, the fixed delay added to the data forfluctuation absorption in the cell disassembly unit 51 can beautomatically suppressed to a minimum limit, and adequate communicationis realized.

This process of optimizing by measuring the effective value D1 can bealso applied in the first to third embodiments, and the same effects asin the fourth embodiment can be obtained. In this case, in the firstembodiment, the reading-start threshold setting unit 16 optimizes thereading-start thresholds TH1 to THn, in the second embodiment, thereading-start wait time setting unit 33 optimizes the reading-start waittimes W1 to Wn, and in the third embodiment, the reading-start thresholdsetting unit 43 optimizes the reading-start thresholds VPTH1 to VPTHm.

In the first to third embodiments, the data interface width betweenfunctional blocks is 8 bits and data is transferred in byte units, butsame effects are obtained by the different data interface widths ortransfer units. The STM interface speed and ATM interface speed are notparticularly limited, and may be any speed. The ATM cell is used as thebasic transfer unit, but similar effects are obtained by other transferunits such as packets of different kinds or lengths other than the ATMcells. As the specific transfer method of data on the STM circuitinterface 62 by cells through the ATM network 63, the structured datatransfer method designated in ITU-T Recommendation I.363.1 is used, butother transfer method having similar function may be also employed.

As described herein, according to one aspect of this invention, the celldisassembly unit stores the data distributed in each time slottemporarily in the buffer provided in each time slot, and absorbsfluctuations of the cell. Therefore, fluctuations can be absorbed ineach time slot constant in communication speed, and the capacity of eachbuffer is always enough at the minimum capacity (the capacity enough toaccommodate communication speed in each time slot) regardless of thecommunication speed of virtual path, and the memory is composed in asimple structure, thereby suppressing both increase of total capacity ofmemory for absorbing fluctuations and complication of memory circuit,and reducing the cost.

According to another aspect of this invention, the cell disassembly unitaccumulates data after start of communication by writing datadistributed in each time slot into the buffer, reads out the data fromthe buffer, parallel to writing, when the data accumulated amount in thebuffer reaches a prescribed amount, and sends out the read data to theSTM circuit interface, and therefore, fluctuations can be absorbed in asimple procedure.

According to still another aspect of this invention, the celldisassembly unit accumulates data after start of communication bywriting data distributed in each time slot into the buffer, reads outthe data from the buffer, parallel to writing, when passing a firstprescribed amount, and sends out the read data to the STM circuitinterface, and therefore, fluctuations can be absorbed in a simpleprocedure.

According to still another aspect of this invention, the prescribedamount or first prescribed time can be set by the setting unit.Therefore, the prescribed amount or first prescribed time can beadjusted depending on the environments of use, thereby decreasingaddition of fixed delay more than necessary or overflow or underflow,and realizing adequate communication.

According to still another aspect of this invention, the measuring unitmeasures fluctuations of the cell, and the setting unit sets the valueof the prescribed amount or first prescribed time on the basis of theresult of measurement by the measuring unit. Therefore, the prescribedamount or first prescribed time can be adjusted automatically andappropriately, so that an adequate communication is realized.

According to still another aspect of this invention, the prescribedamount or first prescribed time is present independently in each buffer,and the cell disassembly unit determines the reading-start timing fromthe buffer independently in each buffer, and therefore the reading-starttiming can be controlled finely in each buffer.

According to still another aspect of this invention, the prescribedamount or first prescribed time is present independently in each virtualpath, and the cell disassembly unit determines the reading-start timingfrom the buffer independently in every one or two or more bufferscorresponding to each virtual path, and therefore it is higher inprobability that the data to be issued in a same frame is actuallyissued in the same frame, thereby realizing adequate communication.

According to still another aspect of this invention, the celldisassembly unit starts reading action from all buffers corresponding tothe virtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in more than a specified number, for example, one or more of buffers outof one or two or more buffers corresponding to a same virtual path.Therefore, in a simple method, the reading-start timing in every one ortwo or more buffers corresponding to each virtual path can becontrolled.

According to still another aspect of this invention, the celldisassembly unit starts reading action from all buffers corresponding tothe virtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in all buffers out of one or two or more buffers corresponding to a samevirtual path, and therefore, in a simple method, the reading-starttiming in every one or two or more buffers corresponding to each virtualpath can be controlled.

According to still another aspect of this invention, the celldisassembly unit once stops, when an underflow occurs in the buffer,reading out from the buffer having the underflow, and resumes readingout when the data accumulated amount reaches again the prescribed amountor passing a second prescribed time after occurrence of underflow, andtherefore if an underflow occurs, a normal communication can berecovered promptly, thereby realizing adequate communication.

According to still another aspect of this invention, the celldisassembly unit, when an underflow occurs in any one of one or two ormore buffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anunderflow occurs, a normal communication can be recovered promptly,thereby realizing adequate communication.

According to still another aspect of this invention, the celldisassembly unit resets, when an overflow occurs in the buffer, thebuffer having the overflow, once stops reading out from this buffer, andresumes reading out when the data accumulated amount reaches again theprescribed amount or passing a second prescribed time after execution ofresetting, and therefore if an overflow occurs, a normal communicationcan be recovered promptly, thereby realizing adequate communication.

According to still another aspect of this invention, the celldisassembly unit, when an overflow occurs in any one of one or two ormore buffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anoverflow occurs, a normal communication can be recovered promptly,thereby realizing adequate communication.

According to still another aspect of this invention, the celldisassembly unit once stops, when an overflow occurs in the buffer,writing into the buffer having the overflow, and resumes writing whenthe data accumulated amount in this buffer decreases to the prescribedamount or passing a second prescribed time after occurrence of overflow,and therefore if an overflow occurs, a normal communication can berecovered promptly, thereby realizing adequate communication.

According to still another aspect of this invention, the celldisassembly unit once stops, when an overflow occurs in the buffer,writing into the buffer having the overflow, and resumes writing whenthe data accumulated amount in this buffer decreases to the prescribedamount or passing a second prescribed time after occurrence of overflow,and therefore if an overflow occurs, a normal communication can berecovered promptly, and therefore if an overflow occurs, a normalcommunication can be recovered promptly, thereby realizing adequatecommunication.

According to still another aspect of this invention, the increasing orextending unit increases the prescribed amount or extends the secondprescribed time when an underflow occurs in the buffer. Therefore,recurrence of underflow can be automatically decreased, therebyrealizing adequate communication.

According to still another aspect of this invention, the increasing orextending unit increases the prescribed amount or extends the secondprescribed time when an overflow occurs in the buffer. Therefore,recurrence of overflow can be automatically decreased, thereby realizingadequate communication.

According to still another aspect of this invention, the storing stepstores the data distributed in each time slot temporarily in the bufferprovided in each time slot, and absorbs fluctuations of the cell.Therefore, fluctuations can be absorbed in each time slot constant incommunication speed, and the capacity of each buffer is always enough atthe minimum capacity (the capacity enough to accommodate communicationspeed in each time slot) regardless of the communication speed ofvirtual path, and the memory is composed in a simple structure, therebysuppressing both increase of total capacity of memory for absorbingfluctuations and complication of memory circuit, and reducing the cost.

According to still another aspect of this invention, the accumulatingstep accumulates data after start of communication by writing datadistributed in each time slot into the buffer, the reading and writingstep reads out the data from the buffer, parallel to writing, when thedata accumulated amount in the buffer at the accumulating step reaches aprescribed amount, and the sending step sends out the read data to theSTM circuit interface. Therefore, fluctuations can be absorbed in asimple procedure.

According to still another aspect of this invention, the accumulatingstep accumulates data after start of communication by writing datadistributed in each time slot into the buffer, the reading and writingstep reads out the accumulated data, parallel to writing, when the datais accumulated for a first prescribed time at the accumulating step, andthe sending step sends out the data read out at the reading and writingstep to the STM circuit interface, and therefore, fluctuations can beabsorbed in a simple procedure.

According to still another aspect of this invention, the prescribedamount or first prescribed time can be set at the setting step.Therefore, the prescribed amount or first prescribed time can beadjusted depending on the environments of use, thereby decreasingaddition of fixed delay more than necessary or overflow or underflow,and realizing adequate communication.

According to still another aspect of this invention, the measuring stepmeasures fluctuations of the cell, and the setting step sets the valueof the prescribed amount or first prescribed time on the basis of theresult of measurement at the measuring step. Therefore, the prescribedamount or first prescribed time can be adjusted automatically andappropriately, thereby realizing a more adequate communication.

According to still another aspect of this invention, the prescribedamount or first prescribed time is present independently in each buffer,and the reading and writing step determines the reading-start timingfrom the buffer independently in each buffer, and therefore thereading-start timing can be controlled finely in each buffer.

According to still another aspect of this invention, the prescribedamount or first prescribed time is present independently in each virtualpath, and the reading and writing step determines the reading-starttiming from the buffer independently in every one or two or more bufferscorresponding to each virtual path, and therefore it is higher inprobability that the data to be issued in a same frame is actuallyissued in the same frame.

According to still another aspect of this invention, the reading andwriting step starts reading action from all buffers corresponding to thevirtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in more than a specified number, for example, one or more of buffers outof one or two or more buffers corresponding to a same virtual path.Therefore, in a simple method, the reading-start timing in every one ortwo or more buffers corresponding to each virtual path can becontrolled.

According to still another aspect of this invention, the reading andwriting step starts reading action from all buffers corresponding to thevirtual path when the data accumulated amount reaches the prescribedamount or passing the prescribed first time from start of communication,in all buffers out of one or two or more buffers corresponding to a samevirtual path, and therefore, in a simple method, the reading-starttiming in every one or two or more buffers corresponding to each virtualpath can be controlled.

According to still another aspect of this invention, the reading andwriting step once stops, when an underflow occurs in the buffer, readingout from the buffer having the underflow, and resumes reading out whenthe data accumulated amount reaches again the prescribed amount orpassing a second prescribed time after occurrence of underflow, andtherefore if an underflow occurs, a normal communication can berecovered promptly, thereby realizing adequate communication.

According to still another aspect of this invention, the reading andwriting step, when an underflow occurs in any one of one or two or morebuffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anunderflow occurs, a normal communication can be recovered promptly,thereby realizing adequate communication.

According to still another aspect of this invention, the reading andwriting step resets, when an overflow occurs in the buffer, the bufferhaving the overflow, once stops reading out from this buffer, andresumes reading out when the data accumulated amount reaches again theprescribed amount or passing a second prescribed time after execution ofresetting, and therefore if an overflow occurs, a normal communicationcan be recovered promptly, thereby realizing adequate communication.

According to still another aspect of this invention, the reading andwriting step, when an overflow occurs in any one of one or two or morebuffers corresponding to a same virtual path, resets all bufferscorresponding to this virtual path, and once stops writing and readingin these buffers, and resumes writing so that the data belonging to asame frame period may be accumulated uniformly at the beginning of thesebuffers, and resumes reading out when the data accumulated amount inthese buffers reaches again the prescribed amount or passing a secondprescribed time after execution of resetting, and therefore if anoverflow occurs, a normal communication can be recovered promptly,thereby realizing adequate communication.

According to still another aspect of this invention, the reading andwriting step once stops, when an overflow occurs in the buffer, writinginto the buffer having the overflow, and resumes writing when the dataaccumulated amount in this buffer decreases to the prescribed amount orpassing a second prescribed time after occurrence of overflow, andtherefore if an overflow occurs, a normal communication can be recoveredpromptly, thereby realizing adequate communication.

According to still another aspect of this invention, the reading andwriting step once stops, when an overflow occurs in the buffer, writinginto the buffer having the overflow, and resumes writing when the dataaccumulated amount in this buffer decreases to the prescribed amount orpassing a second prescribed time after occurrence of overflow, andtherefore if an overflow occurs, a normal communication can be recoveredpromptly, and therefore if an overflow occurs, a normal communicationcan be recovered promptly, thereby realizing adequate communication.

According to still another aspect of this invention, the increasing orextending step increases the prescribed amount or extends the secondprescribed time when an underflow occurs in the buffer, and therefore,recurrence of underflow can be automatically decreased, therebyrealizing adequate communication.

According to still another aspect of this invention, the increasing orextending step increases the prescribed amount or extends the secondprescribed time when an overflow occurs in the buffer, and therefore,occurrence of underflow can be automatically decreased, therebyrealizing adequate communication.

According to still another aspect of this invention, a same prescribedtime can be defined for the first prescribed time and second prescribedtime. Therefore, in the event of overflow or underflow, when the secondprescribed time is extended, the first prescribed time is also extended,thereby decreasing occurrence of under flow after start ofcommunication.

According to still another aspect of this invention, since the method ofthe invention can be executed by the computer, both increase of totalcapacity of the memory for absorbing fluctuations and complication ofmemory control circuit can be suppressed, so that the cost can bereduced.

INDUSTRIAL APPLICABILITY

As described herein, the cell disassembly device, cell disassemblymethod, and computer-readable recording medium recording a program forexecuting this method by a computer are suited to transmission andreception of effective data (effective time slot) on the STM circuithaving plural time slots (TS) divided and multiplexed in time in theframe period through ATM network, by using structured data transfer(SDT) method or the like designated in the ITU-T Recommendation, and arefurther useful for suppressing both increase of total capacity of memoryfor absorbing fluctuations and complication of memory control circuit,and reducing the cost.

1. A cell disassembly device comprising: a cell disassembly unit whichdisassembles an ATM cell received from an ATM circuit interface, extractdata from payload, distributes data in plural STM time slots accordingto a sender, and sends out the distributed data to an STM circuitinterface; and a buffer unit, which includes an input stage and anindependent STM buffer for each STM time slot, wherein the input stageconverts between ATM and STM timing, and each STM buffer operatesaccording to STM timing, wherein said cell disassembly unit stores thedata distributed in each STM time slot temporarily in said STM buffer,and absorbs fluctuations of transferring the ATM cell to the STM timeslots.
 2. The cell disassembly device according to claim 1, wherein saidcell disassembly unit accumulates data after start of communication bywriting data distributed in each STM time slot into the correspondingSTM buffer, reads out the data from said STM buffer, parallel towriting, when the data accumulated amount in said STM buffer reaches aprescribed amount, and sends out the read data to said STM circuitinterface.
 3. The cell disassembly device according to claim 2, furthercomprising a setting unit which sets the prescribed amount or a firstprescribed time for reading out data from said STM buffer.
 4. The celldisassembly device according to claim 3, further comprising a measuringunit which measures fluctuations of the ATM cell, wherein said settingunit sets the value of the prescribed amount or first prescribed time onthe basis of the result of measurement by said measuring unit.
 5. Thecell disassembly device according to claim 2, wherein the prescribedamount or first prescribed time is set independently for each STMbuffer, and said cell disassembly unit determines the reading-starttiming independently in each STM buffer.
 6. The cell disassembly deviceaccording to claim 2, wherein the prescribed amount or first prescribedtime is set independently for each virtual path, and said celldisassembly unit determines the reading-start timing independently foreach set of one or more STM buffers corresponding to each respectivevirtual path.
 7. The cell disassembly device according to claim 6,wherein said cell disassembly unit starts reading out data from all STMbuffers in said buffer unit corresponding to a same virtual path whenthe data accumulated amount reaches the prescribed amount or when theprescribed first time passes from the start of communication in morethan a specified number of STM buffers corresponding to the same virtualpath.
 8. The cell disassembly device according to claim 6, wherein saidcell disassembly unit starts reading out data from all STM buffers insaid buffer unit corresponding to a same virtual path when the dataaccumulated amount reaches the prescribed amount or when the prescribedfirst time passes from the start of communication in all STM bufferscorresponding to the same virtual path.
 9. The cell disassembly deviceaccording to claim 2, wherein said cell disassembly unit stops, when anunderflow occurs in one of the STM buffers, reading out from the STMbuffer having the underflow, and resumes reading out when the dataaccumulated amount reaches again the prescribed amount or when a secondprescribed time passes after occurrence of the underflow.
 10. The celldisassembly device according to claim 1, wherein said cell disassemblyunit accumulates data after start of communication by writing datadistributed in each STM time slot into one of said STM buffers, readsout the data from said STM buffer, parallel to writing, after a firstprescribed time passes, and sends out the read data to the STM circuitinterface.
 11. The cell disassembly device according to claim 10,further comprising a setting unit which sets a prescribed amount or thefirst prescribed time for reading out the data from said STM buffer. 12.The cell disassembly device according to claim 11, further comprising ameasuring unit which measures fluctuations of the ATM cell, wherein saidsetting unit sets the value of the prescribed amount or first prescribedtime on the basis of the result of measurement by said measuring unit.13. The cell disassembly device according to claim 11 wherein theprescribed amount or first prescribed time is set independently for eachSTM buffer, and said cell disassembly unit determines the reading-starttiming independently in each STM buffer.
 14. The cell disassembly deviceaccording to claim 10, wherein the prescribed amount or first prescribedtime is set independently for each virtual path, and said celldisassembly unit determines the reading-start timing independently oreach set of one or more STM buffers corresponding to each respectivevirtual path.
 15. The cell disassembly device according to claim 14,wherein said cell disassembly unit starts reading data from all STMbuffers in said buffer unit corresponding to a same virtual path whenthe data accumulated amount reaches the prescribed amount or when theprescribed first time passes from the start of communication in morethan a specified number of buffers corresponding to the same virtualpath.
 16. The cell disassembly device according to claim 14, whereinsaid cell disassembly unit starts reading action from all STM buffers inthe buffer unit corresponding to same virtual path when the dataaccumulated amount reaches the prescribed amount or when the prescribedfirst time passes from the start of communication in all STM bufferscorresponding to the same virtual path.
 17. The cell disassembly deviceaccording to claim 10, wherein said cell disassembly unit stops, when anunderflow occurs in the STM buffer, reading out from the STM bufferhaving the underflow, and resumes reading out when the data accumulatedamount reaches again the prescribed amount or when a second prescribedtime passes after occurrence of the underflow.
 18. The cell disassemblydevice according to claim 1, wherein the buffer in each STM time slotincludes a configuration that determines the STM frame to which dataread out from the STM time slot is issued without using predeterminedframe boundary information.
 19. A cell disassembly method, the methodcomprising: disassembling an ATM cell received from an ATM circuitinterface, where the disassembling extracts data from payload,distributes data in plural STM time slots according to a sender, andsends out the distributed data to an STM circuit interface; and storingthe data distributed in each STM time slot temporarily in a respectiveSTM buffer, which is implemented in buffer unit for that time slot, andabsorbing fluctuations of transferring the ATM cell to the STM timeslots, wherein an input stage of the buffer unit converts between ATMtiming and STM timing, and each STM buffer operates according to STMtiming.
 20. A computer-readable recording medium recording a computerprogram for causing a computer to execute a cell disassembly method, themethod comprising: disassembling an ATM cell received from an ATMcircuit interface, wherein the disassembling extracts data from payload,distributes data in plural STM time slots according to a sender, andsends out the distributed data to an STM circuit interface; and storingthe data distributed in each STM time slot temporarily in a respectiveSTM buffer, which is implemented in a buffer unit for that time slot,and absorbing fluctuations of transferring the ATM cell to the STM timeslots, wherein an input stage of the buffer unit converts between ATMtiming and STM timing, and each STM buffer operates according to STMtiming.